公开(公告)号：US10956645B2

公开(公告)日：2021-03-23

申请号：US16366918

申请日：2019-03-27

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  G06F30/394 ,  G06F30/39 ,  G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  H01L23/522 ,  H01L23/528 ,  G06F115/08 ,  G06F119/06

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

公开(公告)号：US20180144086A1

公开(公告)日：2018-05-24

申请号：US15432431

申请日：2017-02-14

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: G06F17/50 ,  H01L23/528 ,  H01L23/522

CPC classification number: G06F17/5077 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/66 ,  G06F2217/78 ,  H01L23/5226 ,  H01L23/5286

Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.

公开(公告)号：US10078358B2

公开(公告)日：2018-09-18

申请号：US15171851

申请日：2016-06-02

Applicant: QUALCOMM Incorporated

Inventor： Juan Ochoa Munoz ,  Yuancheng Chris Pan ,  Mikhail Popovich ,  Joon Hyung Chung

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3296

Abstract: A power delivery network (PDN) including a battery, a set of regulators for generating supply voltages, and an integrated circuit (IC) including power rails configured to receive the supply voltages. The IC further includes an IC chip having a set of cores. The power rails includes a larger rail configured to provide a full range of currents, and the other smaller power rails each configured to provide lower range of currents. The IC includes multiplexers having first inputs coupled respectively to the smaller rails, second inputs coupled to the larger rail, and outputs coupled to the cores. When the smaller rail is able to supply the current needed by a core, the multiplexer is configured to couple the smaller rail to the core. When the smaller rail cannot supply the current needed by the core, the multiplexer is configured to couple the larger rail to the core.

公开(公告)号：US09520358B2

公开(公告)日：2016-12-13

申请号：US14744634

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Xiongfei Meng ,  Joon Hyung Chung ,  Yuancheng Christopher Pan

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/06 ,  H01L23/66

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/66 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.

Abstract translation: 包括导电堆叠结构的装置包括在Mx层上的Mx层互连并且在第一轨道上沿第一方向延伸，My层上的My层互连，其中My层是比Mx层低的层， 首先通过耦合在Mx层互连和My层互连之间的堆叠，耦合在Mx层互连和My层互连之间的第二通孔堆叠，在紧邻第一轨道的轨道上沿第一方向延伸的第二Mx层互连 以及在紧邻第一轨道的轨道上沿第一方向延伸的第三M×层互连。 Mx层互连在第二Mx层互连和第三Mx层互连之间。 第二Mx层互连和第三Mx层互连彼此分离。

公开(公告)号：US20190220571A1

公开(公告)日：2019-07-18

申请号：US16366918

申请日：2019-03-27

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: G06F17/50 ,  H01L23/528 ,  H01L23/522

CPC classification number: G06F17/5077 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/66 ,  G06F2217/78 ,  H01L23/5226 ,  H01L23/5286

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

公开(公告)号：US10318694B2

公开(公告)日：2019-06-11

申请号：US15432431

申请日：2017-02-14

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/50 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528

Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.

公开(公告)号：US20170351315A1

公开(公告)日：2017-12-07

申请号：US15171851

申请日：2016-06-02

Applicant: QUALCOMM Incorporated

Inventor： Juan Ochoa Munoz ,  Yuancheng Chris Pan ,  Mikhail Popovich ,  Joon Hyung Chung

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3296

Abstract: A power delivery network (PDN) including a battery, a set of regulators for generating supply voltages, and an integrated circuit (IC) including power rails configured to receive the supply voltages. The IC further includes an IC chip having a set of cores. The power rails includes a larger rail configured to provide a full range of currents, and the other smaller power rails each configured to provide lower range of currents. The IC includes multiplexers having first inputs coupled respectively to the smaller rails, second inputs coupled to the larger rail, and outputs coupled to the cores. When the smaller rail is able to supply the current needed by a core, the multiplexer is configured to couple the smaller rail to the core. When the smaller rail cannot supply the current needed by the core, the multiplexer is configured to couple the larger rail to the core.

公开(公告)号：US09620452B2

公开(公告)日：2017-04-11

申请号：US15346693

申请日：2016-11-08

Applicant: QUALCOMM Incorporated

Inventor： Xiongfei Meng ,  Joon Hyung Chung ,  Yuancheng Christopher Pan

IPC: H01L23/528 ,  H01L23/535 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/66 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.