Invention Grant
- Patent Title: Memory circuit and layout structure of a memory circuit
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Application No.: US14692057Application Date: 2015-04-21
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Publication No.: US09640229B2Publication Date: 2017-05-02
- Inventor: Dao-Ping Wang , Chia-Wei Wang
- Applicant: MediaTek Inc.
- Applicant Address: TW Hsin-Chu
- Assignee: MEDIATEK INC.
- Current Assignee: MEDIATEK INC.
- Current Assignee Address: TW Hsin-Chu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: G11C5/06
- IPC: G11C5/06 ; G11C7/06 ; G11C7/00 ; G11C16/12 ; G11C17/12 ; G11C17/14 ; G11C11/56 ; G11C5/14

Abstract:
A memory circuit includes a transistor, a signal line and a plurality of information lines. The transistor includes a first electrode, a second electrode and a control electrode. The transistor is included in a memory cell. The signal line is connected to the first electrode of the transistor. The voltage on the signal line is programmable. At most one of the information lines is connected to the second electrode of the transistor via a contact. Information stored in the memory cell is coded according to the voltage programmed on the signal line and an option of which information line the contact should connect to the second electrode of the transistor.
Public/Granted literature
- US20160203847A1 MEMORY CIRCUIT AND LAYOUT STRUCTURE OF A MEMORY CIRCUIT Public/Granted day:2016-07-14
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