Invention Grant
- Patent Title: Optimized fast feature detection for vector processors
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Application No.: US15345523Application Date: 2016-11-08
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Publication No.: US09652686B2Publication Date: 2017-05-16
- Inventor: Jayasree Sankaranarayanan , Dipan Kumar Mandal , Prashanth R Viswanath
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Charles A. Brill; Frank D. Cimino
- Priority: IN5510/CHE/2014 20141103
- Main IPC: G06K9/46
- IPC: G06K9/46 ; G06K9/48 ; G06K9/62 ; G06K9/00

Abstract:
This invention enables effective corner detection of pixels of an image using the FAST algorithm using a vector SIMD processor. This invention loads an 8×8 pixel block that includes four 7×7 pixel blocks including the 16 peripheral pixels to be tested for each of four center pixels. This invention rearranges the 64 pixels of the 8×8 block to form a 16 element array for each center pixel preferably using a vector permutation instruction. This invention uses vector SIMD subtraction and compare and vector SIMD addition and compare to make the FAST algorithm comparisons. The N consecutive pixels determinations of the FAST algorithm are made from the results of plural shift and AND operations. The corresponding center pixel is marked a corner or not a corner dependent upon of the results of plural shift and AND operations.
Public/Granted literature
- US20170076173A1 Optimized Fast Feature Detection for Vector Processors Public/Granted day:2017-03-16
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