A resonator includes a laminate, an inductive element on the laminate, and a semiconductor die attached to the inductive element and the laminate. The semiconductor die includes a substrate and a device layout area. The device layout area is separated into a number of device layout sub-areas, each of which has an area between about 1.0 μm2 and 100.0 μm2. By limiting the area of each one of the device layout sub-areas with the charge carrier trap trenches, the total area of the semiconductor die prone to inducement of eddy currents (i.e., the layer of accumulated charge at the interface of the substrate and the device layout area) is reduced, which in turn reduces interference with the magnetic field of the inductive element and thus improves the performance of the resonator.