Invention Grant
- Patent Title: Progressive effort decoder architecture
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Application No.: US14502513Application Date: 2014-09-30
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Publication No.: US09654144B2Publication Date: 2017-05-16
- Inventor: Sivagnanam Parthasarathy , Nicholas Julian Richardson , Patrick Robert Khayat , Mustafa Nazmi Kaynak , Ka Leung Ling , Robert B. Eisenhuth
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/15 ; H03M13/11 ; H03M13/29 ; H03M13/37

Abstract:
A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.
Public/Granted literature
- US20160094247A1 PROGRESSIVE EFFORT DECODER ARCHITECTURE Public/Granted day:2016-03-31
Information query
IPC分类: