Invention Grant
- Patent Title: Layout design system for generating layout design of semiconductor device
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Application No.: US14521928Application Date: 2014-10-23
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Publication No.: US09659130B2Publication Date: 2017-05-23
- Inventor: Jin-Tae Kim , Jae-Woo Seo
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2014-0007788 20140122
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
According to example embodiments, a layout design system includes a processor, a storage module configured to store a standard cell design, and a generation module. The standard cell design includes an active area and a normal gate area on the active area. The generation module is configured to receive the standard cell design, to adjust a width of an active cut design crossing the active area of the standard cell design, and to output a chip design including a design element using the processor. The design element includes the active cut design having the width adjusted.
Public/Granted literature
- US20150205901A1 LAYOUT DESIGN SYSTEM FOR GENERATING LAYOUT DESIGN OF SEMICONDUCTOR DEVICE Public/Granted day:2015-07-23
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