Semiconductor device
    1.
    发明授权

    公开(公告)号:US12199040B2

    公开(公告)日:2025-01-14

    申请号:US17180491

    申请日:2021-02-19

    Abstract: Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.

    Layout design system for generating layout design of semiconductor device

    公开(公告)号:US09659130B2

    公开(公告)日:2017-05-23

    申请号:US14521928

    申请日:2014-10-23

    CPC classification number: G06F17/5072 G06F17/5068

    Abstract: According to example embodiments, a layout design system includes a processor, a storage module configured to store a standard cell design, and a generation module. The standard cell design includes an active area and a normal gate area on the active area. The generation module is configured to receive the standard cell design, to adjust a width of an active cut design crossing the active area of the standard cell design, and to output a chip design including a design element using the processor. The design element includes the active cut design having the width adjusted.

    Semiconductor device and semiconductor system having the same

    公开(公告)号:US12224751B2

    公开(公告)日:2025-02-11

    申请号:US18085185

    申请日:2022-12-20

    Abstract: Disclosed is a semiconductor device which includes at least one flip-flop. The flip-flop includes a first latch that includes a first data path receiving input data in response to a transmission signal and outputting middle data, and a first feedback path feeding back the middle data, and a second latch that includes a second data path receiving the middle data in response to the transmission signal and outputting output data, and a second feedback path feeding back the output data, and at least one of the first feedback path and the second feedback path is disabled prior to the first data path or the second data path.

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