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公开(公告)号:US12199040B2
公开(公告)日:2025-01-14
申请号:US17180491
申请日:2021-02-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyeongyu You , Jisu Yu , Jae-Woo Seo , Seung Man Lim
IPC: H01L23/528 , H01L21/285 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/78 , H01L29/786
Abstract: Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.
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公开(公告)号:US10593701B2
公开(公告)日:2020-03-17
申请号:US15908253
申请日:2018-02-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jae-Woo Seo , Youngsoo Shin
IPC: H01L27/118 , H01L23/528 , G06F17/50 , H01L27/02
Abstract: A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.
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公开(公告)号:US10198592B2
公开(公告)日:2019-02-05
申请号:US15010738
申请日:2016-01-29
Inventor: Jae-Woo Seo , Jung-Hee Cheon , Mi-Ran Kim , Myung-Sun Kim
Abstract: A method for managing data by an electronic device is provided. The method includes receiving first data inputted from a user, generating second data by encrypting the first data using a public key, generating a query comprising the second data, transmitting the query to a server, receiving third data corresponding to the query from the server, generating fourth data by decrypting the third data using a secret key corresponding to the public key, and outputting the fourth data.
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公开(公告)号:US09960768B2
公开(公告)日:2018-05-01
申请号:US15178154
申请日:2016-06-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dal-Hee Lee , Jae-Woo Seo , Min-Ho Park
IPC: H03K19/00 , H03K19/0185 , H03K19/0944 , G06F17/50
CPC classification number: H03K19/0013 , G06F17/5072 , H03K19/018507 , H03K19/018521 , H03K19/0944
Abstract: An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.
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5.
公开(公告)号:US09690896B2
公开(公告)日:2017-06-27
申请号:US15094280
申请日:2016-04-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jae-Woo Seo , Jaeha Lee
IPC: H01L21/00 , G06F17/50 , H01L21/8238 , H01L21/768 , H01L23/528 , H01L27/02
CPC classification number: G06F17/5077 , G06F17/5072 , G06F17/5081 , H01L21/76816 , H01L21/76892 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L23/528 , H01L27/0207
Abstract: A method for manufacturing a semiconductor device is provided. The method includes disposing pre-conductive lines and post-conductive lines for forming first and second cells. The first and second cells are adjacent to each other in a first direction. A first conductive line of the first cell extends in a second direction perpendicular to the first direction and is adjacent to a boundary between the first and second cells. A second conductive line and a third conductive line of the second cell extend in the first direction and are adjacent to the boundary. The second and third conductive lines are respectively disposed on two non-adjacent tracks, among a plurality of tracks that extend in the first direction. The first conductive line intersects one of the two non-adjacent tracks and one track disposed between the two non-adjacent tracks.
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公开(公告)号:US09318607B2
公开(公告)日:2016-04-19
申请号:US14273789
申请日:2014-05-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jae-Woo Seo , Gun-Ok Jung , Min-Su Kim , Sang-Shin Han , Ju-Hyun Kang , Uk-Rae Cho
IPC: H01L23/528 , H01L27/02 , H01L29/78 , H01L23/538 , H01L27/092 , H01L27/12 , H01L27/06 , H01L23/00 , H01L25/10
CPC classification number: H01L29/785 , H01L23/5286 , H01L23/538 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L27/0207 , H01L27/0629 , H01L27/092 , H01L27/0924 , H01L27/1211 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15331 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop.
Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括:第一源电极,被配置为将第一电力轨连接到第一杂质区,第一电源轨耦合到第一电压源;第二源极,被配置为将第二电力轨连接到第二杂质区; 第二电源轨耦合到第二电压源,第一和第二电压源不同,第一和第二杂质区上的栅电极,第一杂质区上的第一漏电极,第二杂质区上的第二漏电极, 连接到所述第一漏电极和所述第二漏极的互连线,所述互连线形成至少一个闭环。
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7.
公开(公告)号:US10033710B2
公开(公告)日:2018-07-24
申请号:US14952134
申请日:2015-11-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jae-Woo Seo , Woo-Chul Shim , Choong-Hoon Lee , Yong-Ho Hwang
Abstract: A first electronic device is provided. The first electronic device includes a transceiver, and a processor configured to encrypt a part of information related to a second communication based on information related to a first communication performed between the first electronic device and a second electronic device and control the transceiver to transmit information related to the second communication to the second electronic device through the transceiver.
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公开(公告)号:US09831877B2
公开(公告)日:2017-11-28
申请号:US15211468
申请日:2016-07-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dal-Hee Lee , Jae-Woo Seo
IPC: H03K19/0185 , H01L27/092 , H03K19/00
CPC classification number: H03K19/018521 , H01L27/0207 , H01L27/092 , H01L27/0928 , H03K19/0013
Abstract: An integrated circuit (IC) includes a first circuit, a first well and a second circuit. The first circuit is disposed on a substrate and configured to shift a first bit signal between a first voltage logic level and a second logic voltage level. The first well is disposed in a cell on the substrate and biased to a first voltage. The first well is spaced apart from a first edge of the cell. The second well is disposed in the cell and biased to a second voltage. The second well is disposed to contact a second edge of the cell opposite to the first edge. The first circuit includes a plurality of transistors respectively disposed in the first and second wells.
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公开(公告)号:US09659130B2
公开(公告)日:2017-05-23
申请号:US14521928
申请日:2014-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jin-Tae Kim , Jae-Woo Seo
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F17/5068
Abstract: According to example embodiments, a layout design system includes a processor, a storage module configured to store a standard cell design, and a generation module. The standard cell design includes an active area and a normal gate area on the active area. The generation module is configured to receive the standard cell design, to adjust a width of an active cut design crossing the active area of the standard cell design, and to output a chip design including a design element using the processor. The design element includes the active cut design having the width adjusted.
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公开(公告)号:US12224751B2
公开(公告)日:2025-02-11
申请号:US18085185
申请日:2022-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Garoom Kim , Jae-Woo Seo
IPC: H03K3/3562 , H03K3/012 , H03K3/037
Abstract: Disclosed is a semiconductor device which includes at least one flip-flop. The flip-flop includes a first latch that includes a first data path receiving input data in response to a transmission signal and outputting middle data, and a first feedback path feeding back the middle data, and a second latch that includes a second data path receiving the middle data in response to the transmission signal and outputting output data, and a second feedback path feeding back the output data, and at least one of the first feedback path and the second feedback path is disabled prior to the first data path or the second data path.
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