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    Electrostatic discharge protection device
    2.
    发明授权
    Electrostatic discharge protection device 有权

    公开(公告)号：US09679886B2

    公开(公告)日：2017-06-13

    申请号：US14509365

    申请日：2014-10-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hyun Yoo ,  Jin-Tae Kim ,  Jong-Sung Jeon

    IPC: H01L27/02 ,  H01L27/06

    CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0285 ,  H01L27/0288 ,  H01L27/0629

    Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of active fins and a plurality of grooves. The ESD protection device includes an insulation layer on the active fins and the grooves, and a gate electrode on the active fins. The ESD protection device includes a first impurity region adjacent to a first side of the gate electrode, and a second impurity region adjacent to a second side of the gate electrode. The second side of the gate electrode may be arranged opposite to the first side. The ESD protection device includes an electrode pattern of a capacitor overlapping the first impurity region, a resistor overlapping the second impurity region, and a connection structure electrically connecting the electrode pattern, the gate electrode, and the resistor to each other.

    Layout design system for generating layout design of semiconductor device
    3.
    发明授权
    Layout design system for generating layout design of semiconductor device 有权

    公开(公告)号：US09659130B2

    公开(公告)日：2017-05-23

    申请号：US14521928

    申请日：2014-10-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin-Tae Kim ,  Jae-Woo Seo

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5068

    Abstract: According to example embodiments, a layout design system includes a processor, a storage module configured to store a standard cell design, and a generation module. The standard cell design includes an active area and a normal gate area on the active area. The generation module is configured to receive the standard cell design, to adjust a width of an active cut design crossing the active area of the standard cell design, and to output a chip design including a design element using the processor. The design element includes the active cut design having the width adjusted.

    Integrated circuits including standard cells and methods of manufacturing the integrated circuits
    5.
    发明授权
    Integrated circuits including standard cells and methods of manufacturing the integrated circuits 有权

    公开(公告)号：US10990740B2

    公开(公告)日：2021-04-27

    申请号：US16378751

    申请日：2019-04-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin-Tae Kim ,  Sung-We Cho ,  Tae-Joong Song ,  Seung-Young Lee ,  Jin-Young Lim

    IPC: G06F30/392 ,  H01L27/02 ,  G06F30/394 ,  G06F30/398

    Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.

    Electrostatic discharge protection device
    6.
    发明授权
    Electrostatic discharge protection device 有权

    公开(公告)号：US10186505B2

    公开(公告)日：2019-01-22

    申请号：US15603969

    申请日：2017-05-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hyun Yoo ,  Jin-Tae Kim ,  Jong-Sung Jeon

    IPC: H01L27/02 ,  H01L27/06

    Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer on the fins. A gate electrode extending in a second direction, an electrode pattern of a capacitor, and a resistor are on the insulation layer. A drain is on a first side of the gate electrode, and a source is on a second side of the gate electrode. A connection structure electrically connects the electrode pattern, the gate electrode and the resistor. The electrode pattern is on the first side or the second side of the gate electrode, and the resistor is on the other of the first side or the second side. At least a portion of the resistor extends in the second direction.

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