Invention Grant
- Patent Title: Die warpage control for thin die assembly
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Application No.: US14796759Application Date: 2015-07-10
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Publication No.: US09659899B2Publication Date: 2017-05-23
- Inventor: Sandeep B. Sane , Shankar Ganapathysubramanian , Jorge Sanchez , Leonel R. Arana , Eric J. Li , Nitin A. Deshpande , Jiraporn Seangatith , Poh Chieh Benny Poon
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/00

Abstract:
Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.
Public/Granted literature
- US20150318258A1 DIE WARPAGE CONTROL FOR THIN DIE ASSEMBLY Public/Granted day:2015-11-05
Information query
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