公开(公告)号：US09394619B2

公开(公告)日：2016-07-19

申请号：US13795042

申请日：2013-03-12

申请人： Intel Corporation

发明人： Rajen S. Sidhu ,  Mukul P. Renavikar ,  Sandeep B. Sane

IPC分类号： H05K1/09 ,  H05K1/03 ,  C25D3/58 ,  C25D5/02 ,  H05K3/42 ,  H05K3/46 ,  C23C18/48

CPC分类号： C25D3/58 ,  C23C18/48 ,  C25D5/02 ,  H05K3/421 ,  H05K3/4644

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.

摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括在封装衬底的电介质材料中形成开口，然后使用电镀工艺在开口中镀覆导电互连结构。 电镀工艺可以包括导电金属和掺杂剂，其包含约0.05至10重量％的重量，其中掺杂剂包括镁，锆和锌中的至少一种。

公开(公告)号：US11417592B2

公开(公告)日：2022-08-16

申请号：US16328617

申请日：2016-09-29

申请人： Intel Corporation

发明人： Omkar G. Karhade ,  Nachiket R. Raravikar ,  Sandeep B. Sane

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a device disposed on first side of substrate and an array of conductive interconnect structures disposed on a second side of the first substrate. The conductive interconnect structures of the array may comprise a solder material, wherein the solder material comprises a low temperature alloying element concentration of less than about 5 percent. A second substrate is coupled to the array of conductive interconnect structures.

公开(公告)号：US20170309578A1

公开(公告)日：2017-10-26

申请号：US15138480

申请日：2016-04-26

申请人： Intel Corporation

发明人： Feras Eid ,  Robert L. Sankman ,  Sandeep B. Sane

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L23/562 ,  H01L21/485 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/3511

摘要： A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.

公开(公告)号：US09299672B2

公开(公告)日：2016-03-29

申请号：US14280110

申请日：2014-05-16

申请人： INTEL CORPORATION

发明人： Sven Albers ,  Georg Seidemann ,  Sonja Koller ,  Stephan Stoeckl ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane

IPC分类号： H01L23/00 ,  H01L23/498

摘要： Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

公开(公告)号：US11901299B2

公开(公告)日：2024-02-13

申请号：US18079753

申请日：2022-12-12

申请人： Intel Corporation

发明人： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC分类号： H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/381

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US11276625B2

公开(公告)日：2022-03-15

申请号：US16328614

申请日：2016-09-29

申请人： Intel Corporation

发明人： Siddarth Kumar ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane ,  Shalabh Tandon

IPC分类号： H01L23/367 ,  H01L23/40 ,  H01L21/48 ,  H01L23/427

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.

公开(公告)号：US20210050306A1

公开(公告)日：2021-02-18

申请号：US16541734

申请日：2019-08-15

申请人： INTEL CORPORATION

发明人： Lauren A. Link ,  Andrew J. Brown ,  Sheng C. Li ,  Sandeep B. Sane

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

摘要： Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.

公开(公告)号：US20190279960A1

公开(公告)日：2019-09-12

申请号：US16349959

申请日：2016-12-14

申请人： Intel Corporation

发明人： Omkar G. Karhade ,  Edvin Cetegen ,  Sandeep B. Sane

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H05K1/18

摘要： Disclosed herein are integrated circuit (IC) packages with plates, as well as related devices and methods. For example, in some embodiments, an IC package may include: a package substrate; a plurality of electrical components secured to a face of the package substrate; and a plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate.

公开(公告)号：US20190148311A1

公开(公告)日：2019-05-16

申请号：US16249457

申请日：2019-01-16

申请人： Intel Corporation

发明人： Feras Eid ,  Robert L. Sankman ,  Sandeep B. Sane

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L23/562 ,  H01L21/485 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/3511

摘要： A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.

公开(公告)号：US09368461B2

公开(公告)日：2016-06-14

申请号：US14280110

申请日：2014-05-16

申请人： INTEL CORPORATION

发明人： Sven Albers ,  Georg Seidemann ,  Sonja Koller ,  Stephan Stoeckl ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/05 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/141 ,  H01L2224/16238 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0373

摘要： Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

摘要翻译： 这里公开了与集成电路（IC）封装一起使用的接触焊盘。 在一些实施例中，本文公开的接触垫可以设置在IC封装的基板上，并且可以包括金属突出部分和金属凹部。 金属突出部和金属凹部中的每一个可以具有焊料接触表面。 金属凹部的焊接接触表面可以与金属突出部的焊接接触表面间隔开。 本文还公开了相关的设备和技术，并且可以要求保护其他实施例。