Invention Grant
- Patent Title: Transistor contacts self-aligned two dimensions
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Application No.: US14926657Application Date: 2015-10-29
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Publication No.: US09660040B2Publication Date: 2017-05-23
- Inventor: Andy Chih-Hung Wei , Guillaume Bouche , Mark A. Zaleski , Tuhin Guha Neogi , Jason E. Stephens , Jongwook Kye , Jia Zeng
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams Morgan, P.C.
- Main IPC: H01L29/94
- IPC: H01L29/94 ; H01L29/417 ; H01L21/768 ; H01L27/088 ; H01L21/8234 ; H01L23/532 ; H01L21/02 ; H01L21/285 ; H01L21/8238 ; H01L27/092 ; H01L29/66 ; H01L29/78
Abstract:
Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.
Public/Granted literature
- US20160049481A1 TRANSISTOR CONTACTS SELF-ALIGNED TWO DIMENSIONS Public/Granted day:2016-02-18
Information query
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