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    METHODS OF FORMING CONDUCTIVE LINES AND VIAS AND THE RESULTING STRUCTURES
    2.
    发明申请
    METHODS OF FORMING CONDUCTIVE LINES AND VIAS AND THE RESULTING STRUCTURES 审中-公开

    公开(公告)号：US20190139823A1

    公开(公告)日：2019-05-09

    申请号：US15804006

    申请日：2017-11-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hsueh-Chung Chen ,  Jason E. Stephens ,  Lars W. Liebmann ,  Guillaume Bouche

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/3213

    Abstract: One illustrative method disclosed herein may include forming first and second via openings and forming conductive material for first and second conductive vias across substantially an entirety of an upper surface of a layer of insulating material and in the via openings. A patterned line etch mask layer is then formed above the conductive material, the etch mask having a first feature corresponding to a first conductive line and a second feature corresponding to a second conductive line, and performing at least one etching process to define the first and second conductive lines that are arranged in a tip-to-tip configuration. In this example, a first edge of the first conductive via is substantially aligned with a first end of the first conductive line and a second edge of the second conductive via is substantially aligned with a second end of the second conductive line.

    Methods of cross-coupling line segments on a wafer
    4.
    发明授权
    Methods of cross-coupling line segments on a wafer 有权
    交叉耦合晶片上的线段的方法

    公开(公告)号：US09472455B2

    公开(公告)日：2016-10-18

    申请号：US14246197

    申请日：2014-04-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jason E. Stephens ,  Lei Yuan ,  Lixia Lei ,  David Pritchard ,  Tuhin Guha Neogi

    IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/02

    CPC classification number: H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207

    Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.

    Abstract translation: 提供了一种用于在晶片上制造交叉耦合线段以用于例如制造两个或多个晶体管的交叉耦合栅极的方法。 该制造包括：使用第一掩模使具有第一侧面突起的第一线段图案化; 以及使用第二掩模用第二侧面突起构图第二线段。 第二线段与第一线段偏移，并且图案化的第二侧突起覆盖图案化的第一侧突起，并且有助于限定连接第一和第二线段的十字绣线段。 该方法还包括在限定来自第一和第二线段和十字绣段的交叉耦合线段时选择性地切割第一和第二线段。

    Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines
    5.
    发明授权
    Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines 有权
    通过用导线代替牺牲线，在金属化层中形成合并线

    公开(公告)号：US09412655B1

    公开(公告)日：2016-08-09

    申请号：US14608377

    申请日：2015-01-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Vikrant Chauhan ,  Andy C. Wei

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/308 ,  H01L21/033

    CPC classification number: H01L21/3081 ,  H01L21/0334 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

    Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.

    Abstract translation: 一种方法包括形成埋在第一介电层中的多条牺牲线。 在形成在第一电介质层上方的硬掩模层中形成线合并开口和线切口。 去除由线合并开口露出的第一电介质层的部分以限定线合并凹槽。 通过线切割开口暴露的所选牺牲线的一部分被去除以在所选牺牲线的第一和第二段之间限定线切割凹槽。 第二介质层形成在线切割凹部中。 硬面膜被去除。 多个牺牲线被导电材料代替，以限定在先前由第一和第二段占据的位置中限定具有第三和第四段的至少一个线，并且在线合并凹槽中限定线路合并导电结构。

    FORMING MERGED LINES IN A METALLIZATION LAYER BY REPLACING SACRIFICIAL LINES WITH CONDUCTIVE LINES
    6.
    发明申请
    FORMING MERGED LINES IN A METALLIZATION LAYER BY REPLACING SACRIFICIAL LINES WITH CONDUCTIVE LINES 有权
    在金属化层中形成合并线，通过用导电线代替真实线

    公开(公告)号：US20160225666A1

    公开(公告)日：2016-08-04

    申请号：US14608377

    申请日：2015-01-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Vikrant Chauhan ,  Andy C. Wei

    IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

    CPC classification number: H01L21/3081 ,  H01L21/0334 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

    Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.

    Abstract translation: 一种方法包括形成埋在第一介电层中的多条牺牲线。 在形成在第一电介质层上方的硬掩模层中形成线合并开口和线切口。 去除由线合并开口露出的第一电介质层的部分以限定线合并凹槽。 通过线切割开口暴露的所选牺牲线的一部分被去除以在所选牺牲线的第一和第二段之间限定线切割凹槽。 第二介质层形成在线切割凹部中。 硬面膜被去除。 多个牺牲线被导电材料代替，以限定在先前由第一和第二段占据的位置中限定具有第三和第四段的至少一个线，并且在线合并凹槽中限定线路合并导电结构。

    Borderless contact formation through metal-recess dual cap integration
    9.
    发明授权
    Borderless contact formation through metal-recess dual cap integration 有权
    无边界接触形成通过金属凹槽双盖整合

    公开(公告)号：US09502528B2

    公开(公告)日：2016-11-22

    申请号：US14469014

    申请日：2014-08-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Mark A. Zaleski ,  Andy Chih-Hung Wei

    IPC: H01L29/66 ,  H01L29/417 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653

    Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).

    Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成第一块掩模。 该第一块掩模覆盖至少一个源/漏（s / d）接触位置的至少一部分。 在未被第一块掩模覆盖的s / d接触位置上形成s / d覆盖层。 该s / d封盖层由第一封盖物质构成。 然后，在半导体结构上形成第二块掩模。 该第二块掩模暴露至少一个门位置。 包括第二封盖物质的栅极覆盖层从暴露的栅极位置移除。 然后沉积金属接触层，其形成与s / d接触位置和栅极接触位置的接触。

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