Invention Grant
- Patent Title: Integrated circuits with dual silicide contacts and methods for fabricating same
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Application No.: US15051734Application Date: 2016-02-24
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Publication No.: US09660075B2Publication Date: 2017-05-23
- Inventor: Shao Ming Koh , Guillaume Bouche , Jeremy A. Wahl , Andy C. Wei
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Lorenz & Kopf, LLP
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L29/78 ; H01L27/092 ; H01L21/311 ; H01L29/45 ; H01L21/8238 ; H01L29/16 ; H01L29/167 ; H01L29/161 ; H01L21/02 ; H01L29/08 ; H01L29/24 ; H01L29/66 ; H01L29/417 ; H01L27/12
Abstract:
Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.
Public/Granted literature
- US20160172493A1 INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME Public/Granted day:2016-06-16
Information query
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