- 专利标题: Protocol including a command-specified timing reference signal
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申请号: US13105798申请日: 2011-05-11
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公开(公告)号: US09665507B2公开(公告)日: 2017-05-30
- 发明人: Ian Shaeffer , Thomas J. Giovannini
- 申请人: Ian Shaeffer , Thomas J. Giovannini
- 申请人地址: US CA Sunnyvale
- 专利权人: Rambus Inc.
- 当前专利权人: Rambus Inc.
- 当前专利权人地址: US CA Sunnyvale
- 主分类号: G06F13/16
- IPC分类号: G06F13/16 ; G06F12/00 ; G11C7/10 ; G11C7/22
摘要:
Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.