Invention Grant
- Patent Title: Lithographic plane check for mask processing
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Application No.: US12976646Application Date: 2010-12-22
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Publication No.: US09671685B2Publication Date: 2017-06-06
- Inventor: Chin-Hsiang Lin , Heng-Jen Lee , I-Hsiung Huang , Chih-Chiang Tu , Chun-Jen Chen , Rick Lai
- Applicant: Chin-Hsiang Lin , Heng-Jen Lee , I-Hsiung Huang , Chih-Chiang Tu , Chun-Jen Chen , Rick Lai
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F1/72 ; G03F1/86

Abstract:
The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.
Public/Granted literature
- US20110161893A1 LITHOGRAPHIC PLANE CHECK FOR MASK PROCESSING Public/Granted day:2011-06-30
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