Invention Grant
- Patent Title: Method of forming memory array and logic devices
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Application No.: US15264457Application Date: 2016-09-13
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Publication No.: US09673208B2Publication Date: 2017-06-06
- Inventor: Jinho Kim , Chien-Sheng Su , Feng Zhou , Xian Liu , Nhan Do , Prateep Tuntasood , Parviz Ghazavi
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L29/66 ; H01L27/11531

Abstract:
A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.
Public/Granted literature
- US20170103991A1 METHOD OF FORMING MEMORY ARRAY AND LOGIC DEVICES Public/Granted day:2017-04-13
Information query
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