公开(公告)号：US11362100B2

公开(公告)日：2022-06-14

申请号：US17069563

申请日：2020-10-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11517 ,  H01L27/11529 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11551

Abstract: Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.

公开(公告)号：US20210193671A1

公开(公告)日：2021-06-24

申请号：US16724010

申请日：2019-12-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/11517 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/78

Abstract: A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

公开(公告)号：US10937794B2

公开(公告)日：2021-03-02

申请号：US16208150

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11521 ,  H01L21/28 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.

公开(公告)号：US10727240B2

公开(公告)日：2020-07-28

申请号：US16028244

申请日：2018-07-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/1156 ,  H01L27/11524 ,  H01L21/266 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

公开(公告)号：US10468428B1

公开(公告)日：2019-11-05

申请号：US15957615

申请日：2018-04-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

公开(公告)号：US10312247B1

公开(公告)日：2019-06-04

申请号：US15933124

申请日：2018-03-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/11524 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28

Abstract: A non-volatile memory cell formed on a semiconductor substrate having an upper surface with an upwardly extending fin with opposing first and second side surfaces. First and second electrodes are in electrical contact with first and second portions of the fin. A channel region of the fin includes portions of the first and second side surfaces that extend between the first and second portions of the fin. A floating gate extends along the first side surface of a first portion of the channel region, where no portion of the floating gate extends along the second side surface. A word line gate extends along the first and second side surfaces of a second portion of the channel region. A control gate is disposed over the floating gate. An erase gate has a first portion disposed laterally adjacent to the floating gate and a second portion disposed vertically over the floating gate.

公开(公告)号：US09673208B2

公开(公告)日：2017-06-06

申请号：US15264457

申请日：2016-09-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Chien-Sheng Su ,  Feng Zhou ,  Xian Liu ,  Nhan Do ,  Prateep Tuntasood ,  Parviz Ghazavi

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/11531

CPC classification number: H01L27/11531 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.

公开(公告)号：US09634019B1

公开(公告)日：2017-04-25

申请号：US15225393

申请日：2016-08-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/66 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/8238 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.

公开(公告)号：US20230290864A1

公开(公告)日：2023-09-14

申请号：US17824812

申请日：2022-05-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L27/11556

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/42328 ,  H01L29/7851 ,  H01L27/11556

Abstract: A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.

公开(公告)号：US11646078B2

公开(公告)日：2023-05-09

申请号：US17199243

申请日：2021-03-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C7/22 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/003 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/79 ,  G11C2213/82 ,  H10B63/30 ,  H10N70/821 ,  H10N70/8418 ,  H10N70/8833

Abstract: Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.