A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output.