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公开(公告)号:US11936382B2
公开(公告)日:2024-03-19
申请号:US16454596
申请日:2019-06-27
发明人: Joyce Cheuk Wai Wong , Dragoljub Ignjatovic , Mikhail Rodionov , Ljubisa Bajic , Stephen V. Kosonocky , Steven J. Kommrusch
IPC分类号: H03L1/02 , H03K3/012 , H03K3/013 , H03K3/0231 , H03K3/03 , H03K5/15 , H03L5/00 , H03L7/085 , H03L7/099 , H03K5/1534
CPC分类号: H03K3/013 , H03K3/012 , H03K3/0231 , H03K3/03 , H03K5/1506 , H03K5/1508 , H03L1/02 , H03L5/00 , H03L7/085 , H03L7/0997 , H03K5/1534
摘要: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
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公开(公告)号:US11846957B1
公开(公告)日:2023-12-19
申请号:US17931384
申请日:2022-09-12
申请人: NXP USA, Inc.
发明人: Xiaoqun Liu , Siamak Delshadpour
摘要: One example discloses a signal driver circuit, including: an input configured to receive an input signal; an output configured to transmit an output signal; a low drop-out voltage regulator (LDO) having a regulated voltage output; a set of voltage-modulated amplifiers having a first input coupled to the regulated voltage output, and a second input configured to receive the input signal; wherein the voltage-modulated amplifier is configured to amplify the input signal and transmit an amplified input signal on the output of the signal driver circuit; a de-emphasis controller, including a set of de-emphasis levels; wherein the de-emphasis controller is configured to selectively switch-on a first subset of the set of voltage-modulated amplifiers and switch-off a second subset of the set of voltage-modulated amplifiers based on the de-emphasis levels.
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公开(公告)号:US11722126B2
公开(公告)日:2023-08-08
申请号:US17463001
申请日:2021-08-31
摘要: A system includes a level shifter coupled to a voltage source, a first transistor, and a second transistor. The system also includes a first current source coupled to the first transistor and the second transistor and configured to bias the first transistor and the second transistor. The system includes a slew detector coupled to the voltage source and to the first current source, where the slew detector is configured to detect a change in voltage of the voltage source, and further configured to provide current to the first current source responsive to detecting the change. The system also includes a second current source coupled in parallel to the first current source, where the second current source is configured to provide current to the first current source responsive to a control signal.
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公开(公告)号:US11502657B2
公开(公告)日:2022-11-15
申请号:US17040516
申请日:2018-07-25
发明人: Xiaofeng Shen , Xingfa Huang , Liang Li , Xi Chen , Mingyuan Xu , Jian'an Wang , Dongbing Fu , Guangbing Chen
摘要: A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.
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公开(公告)号:US20220337231A1
公开(公告)日:2022-10-20
申请号:US17712465
申请日:2022-04-04
发明人: Hyunchul HWANG , Minsu KIM
摘要: A flip flop includes a precharge circuit configured to charge a first node by bridging a power voltage node and the first node, the charging of the first node by the precharge circuit according to a voltage level of a clock signal, the charging of the first node by the precharge circuit based on at least two PMOS transistors arranged in series, a discharge circuit configured to discharge the first node by bridging the first node and a ground node, the discharging of the first node according to an input signal and the clock signal, and a second node configured to be charged or discharged, the charging and the discharging of the second node according to a voltage level of the first node.
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公开(公告)号:US20220255536A1
公开(公告)日:2022-08-11
申请号:US17618439
申请日:2020-06-09
申请人: AMS INTERNATIONAL AG
摘要: An apparatus includes a differential current-to-voltage conversion circuit that includes an input sampling stage circuit, a differential integration and DC signal cancellation stage circuit, and an amplification and accumulator stage circuit. An input common mode voltage of the differential current-to-voltage circuit is independent of an output common mode voltage of the differential current-to-voltage circuit.
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公开(公告)号:US20220109445A1
公开(公告)日:2022-04-07
申请号:US17065382
申请日:2020-10-07
IPC分类号: H03K19/003 , G06F11/18 , H03K3/013
摘要: A triple modular redundancy (TMR) flip-flop includes a set of master-gate-latch circuits including a first set of inputs to receive a first digital signal, and a second set of inputs to receive a clock; and a voting logic circuit including a set of inputs coupled to a set of outputs of the set of master-gate-latch circuits, and an output to generate a second digital signal based on the first digital signal. Another TMR flip-flop includes a set of master-gate-latch circuits to receive a set of digital signals in response to a first edge of a clock, respectively; and latch the set of digital signals in response to a second edge of the clock, respectively; and a voting logic circuit to receive the latched set of digital signals; and generate a second digital signal based on a majority of logic levels of the latched first set of digital signals, respectively.
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公开(公告)号:US20220069808A1
公开(公告)日:2022-03-03
申请号:US17446575
申请日:2021-08-31
发明人: Keunyoung KIM , Hyun KIM , Jaesoon PARK , Sunho CHOI
摘要: A comparator circuit includes: a comparator comprising: a first input terminal receiving an input voltage; a second input terminal receiving a reference voltage; an output terminal outputting an output signal according to a result of a comparison between the input voltage and the reference voltage; and a power supply terminal receiving an operating voltage; and a mode controller applying a first operating voltage and a first reference voltage to the second input terminal and the power supply terminal of the comparator for a predetermined delay time in response to a supply of power being initiated from a power supply, and applying a second operating voltage and a second reference voltage to the second input terminal and the power supply terminal of the comparator in response to the delay time elapsing, wherein the first operating voltage is higher than a ground voltage and is lower than the second operating voltage.
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公开(公告)号:US10931202B2
公开(公告)日:2021-02-23
申请号:US16664475
申请日:2019-10-25
摘要: A method to control a high side switch of a motor drive includes sinking a current of an ON signal to communicate a turn ON of the high side switch. A first current signal, a second current signal, a third current signal, a fourth current signal and a common mode rejection signal are generated in response to the ON signal. The ON signal in a presence of common mode noise is determined by comparing the first current signal and the second current signal. A first output signal is generated in response to determining the ON signal. A drive signal is generated responsive to the first output signal to control the high side switch in response to the ON signal in presence of common mode noise that is caused by a slewing at a half-bridge node.
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公开(公告)号:US10915831B2
公开(公告)日:2021-02-09
申请号:US16719123
申请日:2019-12-18
发明人: Lev Samuel Bishop , Jay Gambetta
摘要: Techniques facilitating reduction and/or mitigation of crosstalk in quantum bit gates of a quantum computing circuit are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a signal generation component that implements a control sequence that comprises a single pulse type for a first quantum bit and at least a second quantum bit of a quantum circuit. The computer-executable components can also comprise a coordination component that synchronizes a first pulse of a first channel of the first quantum bit and at least a second pulse of at least a second channel of the second quantum bit. The coordination component can simultaneously apply the first pulse to the first quantum bit and at least the second pulse to at least the second quantum bit.
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