Invention Grant
- Patent Title: Circuit techniques for efficient scan hold path design
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Application No.: US14528554Application Date: 2014-10-30
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Publication No.: US09678154B2Publication Date: 2017-06-13
- Inventor: Animesh Datta , Qi Ye , Steven James Dillen
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/317 ; G01R31/3177 ; H03K5/133 ; H03K5/134 ; G11C7/10 ; G11C29/32 ; G01R31/3185
Abstract:
In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.
Public/Granted literature
- US20160124043A1 CIRCUIT TECHNIQUES FOR EFFICIENT SCAN HOLD PATH DESIGN Public/Granted day:2016-05-05
Information query
