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    Pulse-generator
    2.
    发明授权
    Pulse-generator 有权

    公开(公告)号：US09979394B2

    公开(公告)日：2018-05-22

    申请号：US15044988

    申请日：2016-02-16

    Applicant: QUALCOMM Incorporated

    Inventor： Qi Ye ,  Animesh Datta ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli

    IPC: H03K3/356 ,  H03K19/003 ,  H03K3/037 ,  H03K3/033 ,  H03K5/04

    CPC classification number: H03K19/00384 ,  H03K3/033 ,  H03K3/0375 ,  H03K5/04

    Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

    CIRCUIT TECHNIQUES FOR EFFICIENT SCAN HOLD PATH DESIGN
    3.
    发明申请
    CIRCUIT TECHNIQUES FOR EFFICIENT SCAN HOLD PATH DESIGN 有权
    用于高效扫描路径设计的电路技术

    公开(公告)号：US20160124043A1

    公开(公告)日：2016-05-05

    申请号：US14528554

    申请日：2014-10-30

    Applicant: QUALCOMM Incorporated

    Inventor： Animesh Datta ,  Qi Ye ,  Steven James Dillen

    IPC: G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318541 ,  G11C7/1057 ,  G11C7/1066 ,  G11C29/32 ,  G11C2029/3202 ,  H03K5/133 ,  H03K5/134

    Abstract: In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.

    Abstract translation: 在一个实施例中，扫描路径中的信号延迟的方法包括以扫描模式延迟扫描路径中的扫描信号，通过将扫描信号传播通过串联耦合的多个延迟器件，其中第一延迟 设备由第一电压供电，延迟装置中的第二个由第二电压供电，第二电压大于第一电压。 该方法还包括在功能模式下禁用延迟设备。

    Area efficient flip-flop with improved scan hold-margin
    7.
    发明授权
    Area efficient flip-flop with improved scan hold-margin 有权

    公开(公告)号：US10033359B2

    公开(公告)日：2018-07-24

    申请号：US14921341

    申请日：2015-10-23

    Applicant: QUALCOMM Incorporated

    Inventor： Qi Ye ,  Animesh Datta

    IPC: H03K3/037 ,  H03K3/356 ,  H03K3/3562

    Abstract: A method and an apparatus for wireless communication are provided. The apparatus having a first latch having a first latch input and first latch output and a second latch having a second latch input, a second latch scan output, and a second latch data output. The second latch input is coupled to the first latch output. The apparatus further includes a selection component configured to select between a data input and a scan input based on a shift input. The selection component is coupled to the first latch input. The selection component includes a first NAND-gate, a second NAND-gate, and an OR-gate.

    Low clock power data-gated flip-flop
    8.
    发明授权
    Low clock power data-gated flip-flop 有权

    公开(公告)号：US09966953B2

    公开(公告)日：2018-05-08

    申请号：US15171487

    申请日：2016-06-02

    Applicant: QUALCOMM Incorporated

    Inventor： Qi Ye ,  Animesh Datta ,  Bo Pang

    IPC: H03K3/037 ,  H03K19/21 ,  H03K19/00

    CPC classification number: H03K19/0016 ,  H03K3/012 ,  H03K3/037 ,  H03K19/21

    Abstract: A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.

    Low overhead hold-violation fixing solution using metal-programable cells
    9.
    发明授权
    Low overhead hold-violation fixing solution using metal-programable cells 有权
    使用金属编程单元的低开销持有违规定位解决方案

    公开(公告)号：US09083325B2

    公开(公告)日：2015-07-14

    申请号：US13918670

    申请日：2013-06-14

    Applicant: QUALCOMM Incorporated

    Inventor： Animesh Datta ,  Qi Ye ,  Chih-Lung Kao

    IPC: G06F7/38 ,  G05B19/045 ,  H03K3/037 ,  H03K3/29

    CPC classification number: H03K3/0375 ,  G05B19/045 ,  H03K3/037 ,  H03K3/29

    Abstract: Techniques for fixing hold violations using metal-programmable cells are described herein. In one embodiment, a system comprises a first flip-flop, a second flip-flop, and a data path between the first and second flip-flops. The system further comprises a metal-programmable cell connected to the data path, wherein the metal-programmable cell is programmed to implement at least one capacitor to add a capacitive load to the data path. The capacitive load adds delay to the data path that prevents a hold violation at one of the first and second flip-flops.

    Abstract translation: 本文描述了使用金属可编程单元固定保持违规的技术。 在一个实施例中，系统包括第一触发器，第二触发器和第一和第二触发器之间的数据通路。 该系统还包括连接到数据路径的金属可编程单元，其中该金属可编程单元被编程为实现至少一个电容器以向该数据路径添加电容性负载。 容性负载增加数据通路的延迟，防止在第一和第二触发器之一处的保持违反。

    NOVEL LOW OVERHEAD HOLD-VIOLATION FIXING SOLUTION USING METAL-PROGRAMABLE CELLS
    10.
    发明申请
    NOVEL LOW OVERHEAD HOLD-VIOLATION FIXING SOLUTION USING METAL-PROGRAMABLE CELLS 有权
    使用金属可编程电池的新型低压保持固定解决方案

    公开(公告)号：US20140368247A1

    公开(公告)日：2014-12-18

    申请号：US13918670

    申请日：2013-06-14

    Applicant: QUALCOMM Incorporated

    Inventor： Animesh Datta ,  Qi Ye ,  Chih-Lung Kao

    IPC: H03K3/356

    CPC classification number: H03K3/0375 ,  G05B19/045 ,  H03K3/037 ,  H03K3/29

    Abstract: Techniques for fixing hold violations using metal-programmable cells are described herein. In one embodiment, a system comprises a first flip-flop, a second flip-flop, and a data path between the first and second flip-flops. The system further comprises a metal-programmable cell connected to the data path, wherein the metal-programmable cell is programmed to implement at least one capacitor to add a capacitive load to the data path. The capacitive load adds delay to the data path that prevents a hold violation at one of the first and second flip-flops.

    Abstract translation: 本文描述了使用金属可编程单元固定保持违规的技术。 在一个实施例中，系统包括第一触发器，第二触发器和第一和第二触发器之间的数据通路。 该系统还包括连接到数据路径的金属可编程单元，其中该金属可编程单元被编程为实现至少一个电容器以向该数据路径添加电容性负载。 容性负载增加数据通路的延迟，防止在第一和第二触发器之一处的保持违反。

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