A wiring substrate includes ceramic layers and a conductive member. The ceramic layers have an uppermost ceramic layer and a lowermost ceramic layer. The conductive member includes an upper conductive layer disposed on an upper surface of the uppermost ceramic layer, an internal conductive layer interposed between the ceramic layers, and a lower conductive layer disposed on a lower surface of the lowermost ceramic layer. The conductive member defines vias electrically connecting the upper conductive layer, the internal conductive layer, and the lower conductive layer. A total number of a first vias connected to the lower conductive layer is larger than a total number of a second vias connected to the upper conductive layer.