Invention Grant
- Patent Title: Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor
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Application No.: US14805827Application Date: 2015-07-22
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Publication No.: US09685457B2Publication Date: 2017-06-20
- Inventor: Stefan Flachowsky , Ralf Illgen
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/66 ; H01L29/06 ; H01L21/3105 ; H01L21/308 ; H01L21/3213 ; H01L29/78 ; H01L21/265 ; H01L21/84 ; H01L21/324

Abstract:
A method includes providing a semiconductor-on-insulator structure including a semiconductor substrate, a layer of electrically insulating material over the semiconductor substrate and a layer of semiconductor material over the layer of electrically insulating material. A first transistor is formed. The formation of the first transistor includes forming a dummy gate structure over the layer of semiconductor material, forming a source region of the first transistor and a drain region of the first transistor in portions of the semiconductor substrate adjacent the dummy gate structure, forming an electrically insulating structure annularly enclosing the dummy gate structure and performing a replacement gate process. The replacement gate process includes removing the dummy gate structure and a portion of the layer of semiconductor material below the dummy gate structure, wherein a recess is formed in the electrically insulating structure. The recess is filled with an electrically conductive material.
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