- Patent Title: High-reliability, low-resistance contacts for nanoscale transistors
-
Application No.: US14584161Application Date: 2014-12-29
-
Publication No.: US09685555B2Publication Date: 2017-06-20
- Inventor: Qing Liu , Nicolas Loubet , Chun-chen Yeh , Ruilong Xie , Xiuyu Cai
- Applicant: STMICROELECTRONICS, INC. , INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc.
- Applicant Address: US TX Coppell KY Grand Cayman US NY Armonk
- Assignee: STMICROELECTRONICS, INC.,GLOBALFOUNDRIES, INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: STMICROELECTRONICS, INC.,GLOBALFOUNDRIES, INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US TX Coppell KY Grand Cayman US NY Armonk
- Agency: Seed IP Law Group LLP
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L29/78 ; H01L29/66 ; H01L29/06 ; H01L21/768

Abstract:
Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.
Public/Granted literature
- US20160190325A1 HIGH-RELIABILITY, LOW-RESISTANCE CONTACTS FOR NANOSCALE TRANSISTORS Public/Granted day:2016-06-30
Information query
IPC分类: