Invention Grant
- Patent Title: Dummy gate technology to avoid shorting circuit
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Application No.: US14742589Application Date: 2015-06-17
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Publication No.: US09698047B2Publication Date: 2017-07-04
- Inventor: Ching-Wen Hung , Chih-Sen Huang , Shih-Fang Tzou , Yi-Wei Chen , Yung-Feng Cheng , Li-Ping Huang , Chun-Hsien Huang , Chia-Wei Huang , Yu-Tse Kuo
- Applicant: United Microelectronics Corporation
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/11 ; H01L21/768 ; H01L29/66 ; H01L27/02

Abstract:
Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
Public/Granted literature
- US20160372476A1 Novel Dummy Gate Technology to Avoid Shorting Circuit Public/Granted day:2016-12-22
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