公开(公告)号：US20160372476A1

公开(公告)日：2016-12-22

申请号：US14742589

申请日：2015-06-17

Applicant: United Microelectronics Corporation

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L27/11 ,  H01L21/768 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

Abstract translation: 提供半导体器件和制造这种半导体器件的方法用于改进的FinFET存储器单元，以避免经常在位单元的金属触点之间发生电短路，其中餐触点位于相邻虚拟边缘单元的虚拟栅极旁边。 在一个实施例中，在衬底表面上的栅极层的图案化期间，使用改进的栅极槽图案来延伸与位线相邻的一个或多个栅极槽的长度，以便图形化和分割靠近金属的伪栅极线 活动存储单元的触点。 在另一个实施例中，在栅极线图案化期间，调整邻近有源存储器单元设置的一个或多个虚拟栅极线之间的距离，使得它们在虚设边缘单元内的位置移位以远离有源存储器的金属触点 细胞。

公开(公告)号：US09620369B2

公开(公告)日：2017-04-11

申请号：US14103827

申请日：2013-12-11

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chieh-Te Chen ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Yi-Po Lin

IPC: H01L21/027 ,  H01L21/8232 ,  H01L21/28 ,  H01L27/06 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L21/28079 ,  H01L21/027 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/8232 ,  H01L27/0629

Abstract: A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed.

公开(公告)号：US09698047B2

公开(公告)日：2017-07-04

申请号：US14742589

申请日：2015-06-17

Applicant: United Microelectronics Corporation

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L29/78 ,  H01L27/11 ,  H01L21/768 ,  H01L29/66 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.