A semiconductor memory device includes a plurality of memory cells, a plurality of word lines and a plurality of bit lines, wherein each memory cell is coupled to a respective word line and bit line. The semiconductor memory device includes a plurality of sense amplifiers, wherein each sense amplifier is coupled to two bit lines. The semiconductor memory device is configured to receive a first positive supply voltage, a second positive supply voltage, and a negative supply voltage, and determine a low level of an amplified voltage based on the negative supply voltage in an operation of amplifying data in a memory cell.