Invention Grant
- Patent Title: Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)
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Application No.: US14627347Application Date: 2015-02-20
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Publication No.: US09704769B2Publication Date: 2017-07-11
- Inventor: Thomas J. Strothmann , Seung Wook Yoon , Yaojian Lin
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/31 ; H01L23/00

Abstract:
A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.
Public/Granted literature
- US20150243575A1 Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP) Public/Granted day:2015-08-27
Information query
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