- 专利标题： Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
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申请号： US15258432申请日： 2016-09-07
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公开(公告)号： US09711421B1公开(公告)日： 2017-07-18
- 发明人: Stephen Lam , Dennis Ciplickas , Tomasz Brozek , Jeremy Cheng , Simone Comensoli , Indranil De , Kelvin Doong , Hans Eisenmann , Timothy Fiscus , Jonathan Haigh , Christopher Hess , John Kibarian , Sherry Lee , Marci Liao , Sheng-Che Lin , Hideki Matsuhashi , Kimon Michaels , Conor O'Sullivan , Markus Rauscher , Vyacheslav Rovner , Andrzej Strojwas , Marcin Strojwas , Carl Taylor , Rakesh Vallishayee , Larg Weiland , Nobuharu Yokoyama
- 申请人： PDF Solutions, Inc.
- 申请人地址： US CA San Jose
- 专利权人： PDF Solutions, Inc.
- 当前专利权人： PDF Solutions, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 David Garrod
- 主分类号： H01L21/66
- IPC分类号： H01L21/66
摘要：
Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, including GATE-snake-open and/or GATE-snake-resistance failure modes. Such processes may involve evaluating Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).
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