- 专利标题： Instruction and logic to monitor loop trip count and remove loop optimizations
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申请号： US13996861申请日： 2012-03-30
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公开(公告)号： US09715388B2公开(公告)日： 2017-07-25
- 发明人: Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
- 申请人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Patent Capital Group
- 国际申请： PCT/US2012/031711 WO 20120330
- 国际公布： WO2013/147896 WO 20131003
- 主分类号： G06F15/00
- IPC分类号： G06F15/00 ; G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F9/32 ; G06F9/30 ; G06F9/38 ; G06F11/34 ; G06F9/45
摘要：
Logic and instruction to monitor loop trip count are disclosed. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.
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