A controller for a solid state drive is proposed. The solid state drive comprises a plurality of memory cells, wherein each memory cell comprises a floating gate transistor for storing a symbol when programmed with a threshold voltage associated with that symbol, and wherein each threshold voltage is variable over the memory cells of the plurality of memory cells thereby defining a corresponding threshold voltage distribution. The controller comprises: an encoding unit for encoding information bits into encoded bits; a mapping unit for mapping the encoded bits into symbols to be stored, each one for being stored into a respective target memory cell, wherein the mapping comprises associating the symbols to be stored with the target memory cells in such a way that the threshold voltage distributions associated with said symbols to be stored define overlapping regions smaller than a predetermined overlapping region indicative of an admitted bit error rate; a demapping unit for demapping read symbols read from the target memory cells and providing metrics indicative of a distance between the threshold voltage distributions associated with the read symbols; a conversion unit for converting the metrics into an indication of the reliability of the read symbols; and a soft decoding unit for soft decoding the read symbols according to the indication of the reliability of the read symbols thereby obtaining the information bits. A corresponding solid state drive is also proposed.