Invention Grant
- Patent Title: 3D non-volatile memory array with sub-block erase architecture
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Application No.: US14820209Application Date: 2015-08-06
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Publication No.: US09721668B2Publication Date: 2017-08-01
- Inventor: Teng-Hao Yeh , Kuo-Pin Chang
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Main IPC: G11C16/14
- IPC: G11C16/14 ; G11C16/04 ; G11C16/08 ; H01L27/24

Abstract:
A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.
Public/Granted literature
- US20170040061A1 MEMORY WITH SUB-BLOCK ERASE ARCHITECTURE Public/Granted day:2017-02-09
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