Invention Grant
- Patent Title: Semiconductor package with reduced via hole width and reduced pad patch and manufacturing method thereof
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Application No.: US14536253Application Date: 2014-11-07
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Publication No.: US09721799B2Publication Date: 2017-08-01
- Inventor: Yu-Lin Shih , Chih-Cheng Lee
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L21/288
- IPC: H01L21/288 ; H01L23/00 ; H01L23/31 ; H01L23/498 ; H01L23/538 ; H01L21/683 ; H01L21/56 ; H01L21/768

Abstract:
The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a dielectric layer, a component, and a first patterned conductive layer. The encapsulation layer has a first surface. The component is within the encapsulation layer and has a front surface and a plurality of pads on the front surface. The dielectric layer is on the first surface of the encapsulation layer, and defines a plurality of via holes; wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second surface opposite the first surface of the encapsulation layer. Each of plurality of via holes extends from the second surface of the dielectric layer to a respective one of the plurality of the pads. The first patterned conductive layer is within the dielectric layer and surrounds the via holes.
Public/Granted literature
- US20160133537A1 SEMICONDUCTOR PACKAGE WITH EMBEDDED COMPONENT AND MANUFACTURING METHOD THEREOF Public/Granted day:2016-05-12
Information query
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