Invention Grant
- Patent Title: High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit
-
Application No.: US15255341Application Date: 2016-09-02
-
Publication No.: US09721849B2Publication Date: 2017-08-01
- Inventor: Derek W. Robinson , Amitava Chatterjee
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L21/8249
- IPC: H01L21/8249 ; H01L27/06 ; H01L29/732 ; H01L29/66 ; H01L29/10 ; H01L21/761 ; H01L21/762 ; H01L29/78

Abstract:
A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.
Public/Granted literature
Information query
IPC分类: