Invention Grant
- Patent Title: Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure
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Application No.: US14514190Application Date: 2014-10-14
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Publication No.: US09721925B2Publication Date: 2017-08-01
- Inventor: Henry D. Bathan , Zigmund R. Camacho , Jairus L. Pisigan
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Pte. Ltd.
- Current Assignee: STATS ChipPAC, Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/56 ; H01L21/768 ; H01L25/10 ; H01L25/18 ; H01L23/00

Abstract:
A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.
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Information query
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