公开(公告)号：US08921161B2

公开(公告)日：2014-12-30

申请号：US13732150

申请日：2012-12-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho

IPC: H01L21/00 ,  H01L23/02 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/821 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01022 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers.

Abstract translation: 半导体器件具有第一半导体管芯和围绕第一半导体管芯沉积的第一密封剂。 在第一半导体管芯和第一密封剂上形成第一绝缘层。 第一导电层形成在第一绝缘层之上，并电连接到第一半导体管芯的接触焊盘。 第二半导体管芯安装到第一绝缘层和第一导电层。 第二密封剂沉积在第二半导体管芯周围。 在第二半导体管芯和第二密封剂上形成第二绝缘层。 第二导电层形成在第二绝缘层之上并电连接到第二半导体管芯的接触焊盘。 多个导电通孔连续地穿过电连接到第一和第二导电层的第一和第二半导体管芯的覆盖区之外的第一和第二密封剂形成。

公开(公告)号：US08866275B2

公开(公告)日：2014-10-21

申请号：US13766646

申请日：2013-02-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Dioscoro A. Merilo ,  Henry D. Bathan ,  Emmanuel A. Espiritu

IPC: H01L23/495 ,  H01L21/00 ,  H01L21/56 ,  H01L25/10 ,  H01L25/03 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/495 ,  H01L21/4832 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/16225 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48157 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/831 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H05K2203/0384 ,  H01L2924/01014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.

Abstract translation: 半导体器件具有衬底，其具有通过衬底形成的多个导电通孔和形成在衬底上的第一导电层。 第一半导体管芯安装在衬底上。 第二半导体管芯可以安装在第一半导体管芯上。 引线框架插入件具有基板和从基板延伸的多个基底引线。 在与基极相对的基板的表面上形成耐蚀刻导电层。 引线框架安装在第一半导体管芯上的衬底上。 密封剂沉积在衬底和第一半导体管芯上。 去除基板，同时保持耐蚀刻导电层，并且基板的与基底引线相对的部分电绝缘基极。 在与基极相对的基板的表面上形成互连结构。

公开(公告)号：US20130341789A1

公开(公告)日：2013-12-26

申请号：US14011491

申请日：2013-08-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Henry D. Bathan ,  Dioscoro A. Merilo ,  Jeffrey D. Punzalan

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/24 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24145 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/83005 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps.

Abstract translation: 通过在铜载体上形成焊料凸块制成半导体器件。 在铜载体中形成焊接捕获压痕以接收焊料凸块。 使用芯片附着粘合剂将半导体管芯安装到铜载体上。 半导体管芯具有形成在其有源表面上的接触焊盘。 封装剂沉积在铜载体，焊料凸块和半导体芯片上。 去除一部分密封剂以暴露焊料凸块和接触垫。 在密封剂上形成导电层以连接焊料凸块和接触焊盘。 导电层作为再分配层工作，以将电信号从焊料凸块路由到接触焊盘。 铜载体被去除。 在导电层和密封剂上形成绝缘层。 多个半导体器件可以堆叠并通过焊料凸块电连接。

公开(公告)号：US20130119559A1

公开(公告)日：2013-05-16

申请号：US13732150

申请日：2012-12-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/821 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01022 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers.

Abstract translation: 半导体器件具有第一半导体管芯和围绕第一半导体管芯沉积的第一密封剂。 在第一半导体管芯和第一密封剂上形成第一绝缘层。 第一导电层形成在第一绝缘层之上，并电连接到第一半导体管芯的接触焊盘。 第二半导体管芯安装到第一绝缘层和第一导电层。 第二密封剂沉积在第二半导体管芯周围。 在第二半导体管芯和第二密封剂上形成第二绝缘层。 第二导电层形成在第二绝缘层之上并电连接到第二半导体管芯的接触焊盘。 多个导电通孔连续地穿过电连接到第一和第二导电层的第一和第二半导体管芯的覆盖区之外的第一和第二密封剂形成。

公开(公告)号：US09397236B2

公开(公告)日：2016-07-19

申请号：US14021208

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Henry D. Bathan ,  Lionel Chien Hui Tay ,  Arnel Senosa Trasporto

IPC: H01L31/02 ,  H01L31/0203 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L31/0203 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/32 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.

公开(公告)号：US20150028496A1

公开(公告)日：2015-01-29

申请号：US14514190

申请日：2014-10-14

Applicant: STATS CHIPPAC, LTD.

Inventor： Henry D. Bathan ,  Zigmund R. Camacho ,  Jairus L. Pisigan

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/81 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

Abstract translation: 通过在第一半导体管芯上形成第一和第二互连结构来制造半导体器件。 在第一管芯附近形成第三互连结构。 第二半导体管芯安装在第二和第三互连结构上。 密封剂沉积在第一和第二管芯以及第一，第二和第三互连结构上。 第二管芯的背面基本上与第一互连结构共面，并且第一半导体管芯的背面基本上与第三互连结构共面。 第一互连结构具有与第二互连结构的高度和第二管芯的厚度的组合基本相同的高度。 第三互连结构具有与第二互连结构的高度和第一管芯的厚度的组合基本相同的高度。

公开(公告)号：US20140011315A1

公开(公告)日：2014-01-09

申请号：US14021208

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Henry D. Bathan ,  Lionel Chien Hui Tay ,  Arnel Senosa Trasporto

IPC: H01L31/0203

CPC classification number: H01L31/0203 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/32 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.

Abstract translation: 通过提供具有光学活性区域的半导体管芯制造半导体器件，提供具有多个接触焊盘的引线框架或预成型层叠基板和设置在接触焊盘之间的透光材料，将半导体管芯附接到引线框架 光学活性区域与透光材料对准以提供到光学有效区域的光传输路径，并且在半导体管芯和引线框架之间设置底部填充材料。 透光材料包括用于防止底部填充材料阻挡光传输路径的升高区域。 升高区域包括围绕光传输路径的堤坝，粘合环，或者光传输路径本身可以是高架区域。 可以在大坝上设置粘合环。 填充材料可以设置在透光材料和接触垫之间。

公开(公告)号：USRE47923E1

公开(公告)日：2020-03-31

申请号：US15058005

申请日：2016-03-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Frederick R. Dahilig ,  Lionel Chien Hui Tay ,  Arnel Senosa Trasporto ,  Henry Descalzo Bathan

IPC: H01L23/24 ,  H01L23/28 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03 ,  H01L25/10

Abstract: A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.

公开(公告)号：US09330994B2

公开(公告)日：2016-05-03

申请号：US14228531

申请日：2014-03-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Bartholomew Liao ,  Sheila Marie L. Alvarez ,  HeeJo Chi ,  Kelvin Dao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/3107 ,  H01L21/4846 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. An insulating layer is formed over the semiconductor die and encapsulant. A first channel including a first conductive surface is formed in the insulating layer by laser radiation. A laser-activated catalyst is infused in the insulating layer to form the first conductive surface in the first channel upon laser radiation. A vertical interconnect is formed through the encapsulant. A first conductive layer is formed in the first channel over the first conductive surface. A second channel including a second conductive surface is formed in the encapsulant by laser radiation. The catalyst is infused in the encapsulant to form the second conductive surface in the second channel upon laser radiation. A second conductive layer is formed in the second channel over the second conductive surface. An interconnect structure is formed over the first conductive layer.

Abstract translation: 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 在半导体管芯和密封剂上形成绝缘层。 通过激光辐射在绝缘层中形成包括第一导电表面的第一通道。 在绝缘层中注入激光激活的催化剂，以在激光辐射时在第一通道中形成第一导电表面。 通过密封剂形成垂直互连。 第一导电层在第一通道上形成在第一导电表面上。 通过激光辐射在密封剂中形成包括第二导电表面的第二通道。 催化剂注入到密封剂中以在激光辐射下在第二通道中形成第二导电表面。 第二导电层在第二通道上形成在第二导电表面上。 在第一导电层上形成互连结构。

公开(公告)号：US09257357B2

公开(公告)日：2016-02-09

申请号：US13906667

申请日：2013-05-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Frederick R. Dahilig ,  Zigmund R. Camacho ,  Lionel Chien Hui Tay ,  Dioscoro A. Merilo

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/36 ,  H01L23/34 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/433 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/3672 ,  H01L23/4334 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.