Invention Grant
- Patent Title: Methods and apparatus for doped SiGe source/drain stressor deposition
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Application No.: US15134935Application Date: 2016-04-21
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Publication No.: US09722082B2Publication Date: 2017-08-01
- Inventor: Chao-Hsuing Chen , Ling-Sung Wang , Chi-Yen Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L21/02 ; H01L29/08 ; H01L29/167
Abstract:
A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.
Public/Granted literature
- US20160240673A1 Methods and Apparatus for Doped SiGe Source/Drain Stressor Deposition Public/Granted day:2016-08-18
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