Invention Grant
- Patent Title: Photo pattern method to increase via etching rate
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Application No.: US15351774Application Date: 2016-11-15
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Publication No.: US09741607B2Publication Date: 2017-08-22
- Inventor: Zheng-Chang Mu , Cheng-Wei Lin , Kuang-Wen Liu
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Alston & Bird, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L23/48 ; H01L21/311 ; H01L21/321

Abstract:
Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.
Public/Granted literature
- US20170062270A1 PHOTO PATTERN METHOD TO INCREASE VIA ETCHING RATE Public/Granted day:2017-03-02
Information query
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