Invention Grant
- Patent Title: Integrated interposer solutions for 2D and 3D IC packaging
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Application No.: US14586580Application Date: 2014-12-30
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Publication No.: US09741649B2Publication Date: 2017-08-22
- Inventor: Hong Shen , Charles G. Woychik , Arkalgud R. Sitaram , Guilian Gao
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: INVENSAS CORPORATION
- Current Assignee: INVENSAS CORPORATION
- Current Assignee Address: US CA San Jose
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/498 ; H01L25/16 ; H01L23/31 ; H01L21/48 ; H01L21/56 ; H01L23/538 ; H01L25/065 ; H01L23/10 ; H01L23/13

Abstract:
An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.
Public/Granted literature
- US20150357272A1 INTEGRATED INTERPOSER SOLUTIONS FOR 2D AND 3D IC PACKAGING Public/Granted day:2015-12-10
Information query
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