公开(公告)号：US10014243B2

公开(公告)日：2018-07-03

申请号：US15403679

申请日：2017-01-11

申请人： Invensas Corporation

发明人： Hong Shen ,  Liang Wang ,  Gabriel Z. Guevara ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

摘要： An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

公开(公告)号：US09865675B2

公开(公告)日：2018-01-09

申请号：US15207837

申请日：2016-07-12

申请人： Invensas Corporation

发明人： Liang Wang ,  Rajesh Katkar ,  Hong Shen ,  Cyprian Emeka Uzoh

IPC分类号： H01L49/02

CPC分类号： H01L28/65 ,  H01L28/90 ,  H01L28/92 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00012

摘要： In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

公开(公告)号：US09825002B2

公开(公告)日：2017-11-21

申请号：US15208985

申请日：2016-07-13

申请人： Invensas Corporation

发明人： Rajesh Katkar ,  Reynaldo Co ,  Scott McGrath ,  Ashok S. Prabhu ,  Sangil Lee ,  Liang Wang ,  Hong Shen

IPC分类号： H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0652 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2225/06506 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/19

摘要： A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.

公开(公告)号：US20170317019A1

公开(公告)日：2017-11-02

申请号：US15651826

申请日：2017-07-17

申请人： INVENSAS CORPORATION

发明人： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC分类号： H01L23/498 ,  H01L23/10 ,  H01L23/13 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/16

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/56 ,  H01L23/10 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83

摘要： An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

公开(公告)号：US09741649B2

公开(公告)日：2017-08-22

申请号：US14586580

申请日：2014-12-30

申请人： Invensas Corporation

发明人： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/16 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L23/10 ,  H01L23/13

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/56 ,  H01L23/10 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83

摘要： An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

公开(公告)号：US09741620B2

公开(公告)日：2017-08-22

申请号：US14749529

申请日：2015-06-24

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC分类号： H01L21/00 ,  H01L21/70 ,  H01L21/82 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

CPC分类号： H01L21/82 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L24/98 ,  H01L2224/04105 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512

摘要： A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

公开(公告)号：US09666559B2

公开(公告)日：2017-05-30

申请号：US14809036

申请日：2015-07-24

申请人： Invensas Corporation

发明人： Liang Wang ,  Rajesh Katkar ,  Hong Shen

IPC分类号： H01L21/44 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  B81B7/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768 ,  B81C1/00 ,  H01L23/31 ,  H01L25/10

CPC分类号： H01L24/09 ,  B81B7/008 ,  B81B2207/07 ,  B81C1/0023 ,  H01L21/565 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/34 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/89 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/33517 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/80001 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92133 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

摘要： In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F; “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

公开(公告)号：US20170099474A1

公开(公告)日：2017-04-06

申请号：US15280661

申请日：2016-09-29

申请人： Invensas Corporation

发明人： Hong Shen ,  Liang Wang ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC分类号： H04N9/43 ,  H04N9/097 ,  H04N9/04 ,  G06T1/20 ,  H04N5/374 ,  H01L31/0232 ,  G02B27/10 ,  H01L27/146 ,  H01L31/0304 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/032 ,  H04N5/33 ,  H04N9/76

CPC分类号： H04N9/43 ,  G02B27/1013 ,  G06T1/20 ,  H01L27/1462 ,  H01L27/14634 ,  H01L27/14645 ,  H01L27/1465 ,  H01L27/14685 ,  H01L27/1469 ,  H01L31/02322 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/032 ,  H04N5/332 ,  H04N5/374 ,  H04N9/045 ,  H04N9/097 ,  H04N9/76

摘要： HD color video using monochromatic CMOS image sensors integrated in a 3D package is provided. An example 3DIC package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. Multiple monochromatic CMOS image sensors are each coupled to one of the multiple light outputs to sense a monochromatic image stream at a respective component wavelength of the received light. Each monochromatic CMOS image sensor is specially constructed, doped, controlled, and tuned to its respective wavelength of light. A parallel processing integrator or interposer chip heterogeneously combines the respective monochromatic image streams into a full-spectrum color video stream, including parallel processing of an infrared or ultraviolet stream. The parallel processing of the monochromatic image streams provides reconstruction to HD or 4K HD color video at low light levels. Parallel processing to one interposer chip also enhances speed, spatial resolution, sensitivity, low light performance, and color reconstruction.

公开(公告)号：US09583426B2

公开(公告)日：2017-02-28

申请号：US14533728

申请日：2014-11-05

申请人： Invensas Corporation

发明人： Hong Shen ,  Liang Wang ,  Gabriel Z. Guevara ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

IPC分类号： H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00

CPC分类号： H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

摘要： An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

摘要翻译： 插入器（110）在顶部和/或底部表面处具有用于连接到电路模块（例如IC 112）的接触焊盘。 插入器包括由多层（110.i）制成的衬底。 每个层可以是具有电路的衬底（110S），可能是陶瓷衬底。 基板垂直延伸。 在由对应于插入层的垂直层（310.i）制成的单个结构（310）中制造多个插入件。 沿着水平面（314）切割结构以提供插入件。 在切割之前和所有基板彼此附接之前，可以在基板表面上形成插入件的垂直导线（类似于贯穿基板通孔）。 因此，不需要对垂直导线进行贯通基板孔。 在基板彼此附接之前，也可以在基板表面上形成非垂直特征。 还提供了其他实施例。

公开(公告)号：US09508638B2

公开(公告)日：2016-11-29

申请号：US14833979

申请日：2015-08-24

申请人： INVENSAS CORPORATION

发明人： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC分类号： H01L21/02 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

摘要： A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.