Invention Grant
- Patent Title: 3D chip-on-wafer-on-substrate structure with via last process
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Application No.: US14444681Application Date: 2014-07-28
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Publication No.: US09754918B2Publication Date: 2017-09-05
- Inventor: Chen-Hua Yu , Ming-Fa Chen , Wen-Ching Tsai , Sung-Feng Yeh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L25/065 ; H01L23/538 ; H01L23/00 ; H01L23/48 ; H01L21/768

Abstract:
Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
Public/Granted literature
- US20150325520A1 3D CHIP-ON-WAFER-ON-SUBSTRATE STRUCTURE WITH VIA LAST PROCESS Public/Granted day:2015-11-12
Information query
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