-
公开(公告)号:US12125821B2
公开(公告)日:2024-10-22
申请号:US18080661
申请日:2022-12-13
发明人: Ming-Fa Chen , Sung-Feng Yeh , Tzuan-Horng Liu , Chao-Wen Shih
CPC分类号: H01L25/0652 , H01L21/563 , H01L21/78 , H01L23/3121 , H01L23/481 , H01L24/97 , H01L25/50 , H01L2225/06541
摘要: A package includes an integrated circuit. The integrated circuit includes a first chip, a dummy chip, a second chip, and a third chip. The first chip includes a semiconductor substrate that extends continuously from an edge of the first chip to another edge of the first chip. The dummy chip is disposed over the first chip and includes a semiconductor substrate that extends continuously from an edge of the dummy chip to another edge of the dummy chip. Sidewalls of the first chip are aligned with sidewalls of the dummy chip. The second chip and the third chip are sandwiched between the first chip and the dummy chip. A thickness of the second chip is substantially equal to a thickness of the third chip.
-
公开(公告)号:US12094852B2
公开(公告)日:2024-09-17
申请号:US17575659
申请日:2022-01-14
发明人: Ming-Fa Chen , Sung-Feng Yeh , Tzuan-Horng Liu , Chao-Wen Shih
IPC分类号: H01L25/00 , H01L21/56 , H01L23/31 , H01L23/367 , H01L25/065
CPC分类号: H01L25/0657 , H01L21/56 , H01L23/3107 , H01L23/3675 , H01L25/50
摘要: A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.
-
公开(公告)号:US12057438B2
公开(公告)日:2024-08-06
申请号:US17827990
申请日:2022-05-30
发明人: Chen-Hua Yu , Hsien-Wei Chen , Ming-Fa Chen , Sung-Feng Yeh , Tzuan-Horng Liu
IPC分类号: H01L25/065 , H01L21/56 , H01L21/768 , H01L23/31 , H01L23/538
CPC分类号: H01L25/0657 , H01L21/56 , H01L21/76802 , H01L23/31 , H01L23/5384 , H01L23/5385 , H01L23/5386
摘要: A die stack structure including a first die, an encapsulant, a redistribution layer and a second die is provided. The encapsulant laterally encapsulates the first die. The redistribution layer is disposed below the encapsulant, and electrically connected with the first die. The second die is disposed between the redistribution layer and the first die, wherein the first and second dies are electrically connected with each other, the second die comprises a body portion having a first side surface, a second side surface and a curved side surface therebetween, and the curved side surface connects the first side surface and the second side surface.
-
公开(公告)号:US12046579B2
公开(公告)日:2024-07-23
申请号:US17344928
申请日:2021-06-10
发明人: Ming-Fa Chen , Chao-Wen Shih , Hsien-Wei Chen , Sung-Feng Yeh , Tzuan-Horng Liu
IPC分类号: H01L25/065 , H01L21/304 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/31 , H01L23/538 , H01L23/544 , H01L27/12
CPC分类号: H01L25/0657 , H01L21/304 , H01L21/56 , H01L23/3157 , H01L23/5384 , H01L23/544 , H01L24/05 , H01L21/6835 , H01L27/1266 , H01L2224/0231 , H01L2224/02372 , H01L2224/80203 , H01L2224/8084 , H01L2225/06541
摘要: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.
-
公开(公告)号:US20240021584A1
公开(公告)日:2024-01-18
申请号:US18362973
申请日:2023-08-01
发明人: Ming-Fa Chen , Chao-Wen Shih , Min-Chien Hsiao , Nien-Fang Wu , Sung-Feng Yeh , Tzuan-Horng Liu
IPC分类号: H01L25/065 , H01L23/31 , H01L23/48 , H01L23/00 , H01L21/304 , H01L21/78
CPC分类号: H01L25/0657 , H01L23/3157 , H01L23/481 , H01L24/05 , H01L21/3043 , H01L24/80 , H01L24/94 , H01L21/78 , H01L2224/80001
摘要: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.
-
公开(公告)号:US11855042B2
公开(公告)日:2023-12-26
申请号:US17696591
申请日:2022-03-16
发明人: Ming-Fa Chen , Wen-Chih Chiou , Sung-Feng Yeh
IPC分类号: H01L25/065 , H01L23/31 , H01L23/48 , H01L23/00 , H01L25/00 , H01L21/56 , H01L23/538 , H01L25/10
CPC分类号: H01L25/0655 , H01L21/565 , H01L23/3121 , H01L23/3142 , H01L23/481 , H01L23/5386 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/73 , H01L25/0652 , H01L25/50 , H01L23/3128 , H01L24/32 , H01L24/81 , H01L24/92 , H01L25/105 , H01L2224/0231 , H01L2224/02379 , H01L2224/13024 , H01L2224/16227 , H01L2224/18 , H01L2224/24137 , H01L2224/32225 , H01L2224/73204 , H01L2224/73259 , H01L2224/80001 , H01L2225/06541 , H01L2225/06548 , H01L2225/06565 , H01L2924/15192
摘要: A method of manufacturing a semiconductor structure includes following operations. A substrate is provided. A first die is disposed over the substrate. A second die is provided. The second die includes a via extended within the second die. The second die is disposed over the substrate. A molding is formed around the first die and second die. An interconnect structure is formed. The interconnect structure includes a dielectric layer and a conductive member. The dielectric layer is disposed over the molding, the first die and the second die. The conductive member is surrounded by the dielectric layer. The via is formed by removing a portion of the second die to form a recess extended within the second die and disposing a conductive material into the recess.
-
公开(公告)号:US20230307410A1
公开(公告)日:2023-09-28
申请号:US18327851
申请日:2023-06-01
发明人: Sung-Feng Yeh , Hsien-Wei Chen , Ming-Fa Chen
IPC分类号: H01L23/00 , H01L21/768 , H01L21/306 , H01L21/3105 , H01L23/31 , H01L23/48 , H01L25/00 , H01L21/56
CPC分类号: H01L24/33 , H01L21/76898 , H01L21/30625 , H01L21/31053 , H01L24/05 , H01L23/3128 , H01L23/3135 , H01L23/481 , H01L24/32 , H01L25/50 , H01L21/561 , H01L2224/33051 , H01L2224/02331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05569 , H01L24/13 , H01L2224/13024 , H01L2224/32221 , H01L2224/32057
摘要: A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.
-
公开(公告)号:US20230307306A1
公开(公告)日:2023-09-28
申请号:US17702820
申请日:2022-03-24
发明人: Ming-Fa Chen , Ta-Hao Sung , Sung-Feng Yeh
IPC分类号: H01L23/31 , H01L21/56 , H01L25/00 , H01L25/065 , H01L23/24
CPC分类号: H01L23/3185 , H01L21/568 , H01L25/50 , H01L25/0655 , H01L23/3192 , H01L25/0652 , H01L23/24 , H01L24/32
摘要: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes first semiconductor dies spaced apart from one another, second semiconductor dies stacked upon the first semiconductor dies with a one-to-one correspondence and electrically coupled to the first semiconductor dies, a first composite structure laterally interposed between two first semiconductor dies, a second composite structure laterally interposed between two second semiconductor dies, and a support substrate bonded to the second semiconductor dies and the second composite structure. The first composite structure includes a first material layer adjoining sidewalls of the two first semiconductor dies and a second material layer connected to and different from the first material layer. The second composite structure includes a third material layer adjoining sidewalls of the two second semiconductor dies and a fourth material layer connected to and different from the third material layer.
-
公开(公告)号:US11742297B2
公开(公告)日:2023-08-29
申请号:US17338676
申请日:2021-06-04
发明人: Ming-Fa Chen , Nien-Fang Wu , Sung-Feng Yeh , Tzuan-Horng Liu , Chao-Wen Shih
IPC分类号: H01L23/538 , H01L23/00 , H01L25/065 , H01L21/48 , H01L21/56 , H01L25/00 , H01L23/31
CPC分类号: H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L23/3128 , H01L23/5383 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/214 , H01L2225/06524 , H01L2225/06548 , H01L2225/06562 , H01L2225/06586 , H01L2924/19041 , H01L2924/19105
摘要: A semiconductor package includes a first die, a plurality of second dies and a through via. The second dies are disposed over and electrically connected to the first die. The through via is disposed between the second dies and electrically connected to the first die. The through via includes a first portion having a first width and a second portion having a second width different from the first width and disposed between the first portion and the first die. The first portion includes a first seed layer and a first conductive layer, and the first seed layer is disposed aside an interface between the first portion and the second portion.
-
公开(公告)号:US11728275B2
公开(公告)日:2023-08-15
申请号:US17206117
申请日:2021-03-18
发明人: Ming-Fa Chen , Hsien-Wei Chen , Jie Chen , Sung-Feng Yeh
IPC分类号: H01L23/538 , H01L25/065 , H01L21/78 , H01L23/31 , H01L23/544
CPC分类号: H01L23/5384 , H01L21/78 , H01L23/31 , H01L23/544 , H01L25/0657 , H01L2224/0401
摘要: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first device die and a second device die. The first device die includes first bonding pads at a front surface of the first device die. The second device die is bonded on the first device die, and includes die regions and a scribe line region connecting the die regions with one another. The die regions respectively comprise second bonding pads at a front surface of the second device die. The second bonding pads are respectively in contact with one of the first bonding pads.
-
-
-
-
-
-
-
-
-