Invention Grant
- Patent Title: Semiconductor device including buffer circuit and level shifter circuit, and electronic device including the same
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Application No.: US14967592Application Date: 2015-12-14
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Publication No.: US09755643B2Publication Date: 2017-09-05
- Inventor: Hiroki Inoue , Takanori Matsuzaki , Shuhei Nagatsuka , Takahiko Ishizu , Tatsuya Onuki
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2014-254393 20141216
- Main IPC: H03L5/00
- IPC: H03L5/00 ; H03K19/0185 ; H03K19/00

Abstract:
To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. The semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. When the semiconductor device returns to a normal state, the second potential is supplied, so that the potential of a node in the level shifter circuit increases. To utilize the increase in the second potential or suppress malfunction due to the increase in the potential, capacitors are provided in the level shifter circuit. This inhibits unexpected operation of a transistor in the level shifter circuit.
Public/Granted literature
- US20160173097A1 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE Public/Granted day:2016-06-16
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