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    Storage device, semiconductor device, electronic component, and electronic device
    2.
    发明授权
    Storage device, semiconductor device, electronic component, and electronic device 有权

    公开(公告)号：US11366507B2

    公开(公告)日：2022-06-21

    申请号：US17104460

    申请日：2020-11-25

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Shuhei Maeda ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Kiyoshi Kato

    IPC分类号： G11C14/00 ,  G06F1/3234 ,  G11C5/14 ,  G11C16/30

    摘要： To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

    Memory device
    3.
    发明授权
    Memory device 有权

    公开(公告)号：US11270997B2

    公开(公告)日：2022-03-08

    申请号：US16757025

    申请日：2018-11-19

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Tatsuya Onuki ,  Yuki Okamoto ,  Hisao Ikeda ,  Shuhei Nagatsuka

    IPC分类号： H01L27/00 ,  H01L29/00 ,  H01L27/105 ,  H01L27/12 ,  H01L29/786

    摘要： A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are stacked. One of two bit lines of a first bit line pair is electrically connected to A memory cells of the first cell array, and the other of the two bit lines of the first bit line pair is electrically connected to D memory cells of the second cell array. One of two bit lines of a second bit line pair is electrically connected to B memory cells of the first cell array and F memory cells of the second cell array, and the other of the two bit lines of the second bit line pair is electrically connected to C memory cells of the first cell array and E memory cells of the second cell array. The first bit line pairs and the second bit line pairs are alternately provided.

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11114449B2

    公开(公告)日：2021-09-07

    申请号：US16810902

    申请日：2020-03-06

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

    IPC分类号： H01L29/10 ,  H01L27/115 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  H01L29/786 ,  H01L27/06 ,  H01L27/1156 ,  H01L27/11551 ,  H01L29/24 ,  G11C11/408

    摘要： [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
    [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09666722B2

    公开(公告)日：2017-05-30

    申请号：US14603632

    申请日：2015-01-23

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Daisuke Matsubayashi ,  Yoshiyuki Kobayashi ,  Shuhei Nagatsuka ,  Yutaka Shionoiri

    IPC分类号： H01L29/786

    CPC分类号： H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

    摘要： A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.

    Semiconductor device and driving method thereof
    6.
    发明授权
    Semiconductor device and driving method thereof 有权
    半导体装置及其驱动方法

    公开(公告)号：US09496285B2

    公开(公告)日：2016-11-15

    申请号：US14962809

    申请日：2015-12-08

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Shuhei Nagatsuka

    IPC分类号： H01L27/12 ,  H01L29/786

    CPC分类号： H01L27/1225 ,  H01L27/1255

    摘要： The semiconductor device includes a transistor, first to N-th switches (N is a natural number of three or more), and first to (N−1)-th capacitors. A first terminal of the first capacitor (or a J-th capacitor) is electrically connected to a gate of the transistor (or a second terminal of a (J−1)-th capacitor (J is a natural number of two or more and (N−1) or less)). A first (or K-th) potential is supplied to the gate of the transistor through the first switch (or a second terminal of a (K−1)-th capacitor through a K-th switch (K is a natural number of two or more and N or less)). A capacitance value of the first capacitor is preferably equal to a gate capacitance value of the transistor, and a capacitance value of the J-th capacitor is preferably equal to a capacitance value of the (J−1)-th capacitor.

    摘要翻译： 半导体器件包括晶体管，第一至第N开关（N为三个以上的自然数）以及第一至第（N-1）个电容器。 第一电容器（或第J电容器）的第一端子电连接到晶体管的栅极（或第（J-1）个电容器的第二端子（J为两个以上的自然数， （N-1）以下））。 第一（或第K）个电位通过第一开关（或第（K-1）个电容器的第二端子通过第K开关提供给晶体管的栅极（K是自然数为2） 以上且N以下））。 第一电容器的电容值优选等于晶体管的栅极电容值，并且第J电容器的电容值优选等于第（J-1）个电容器的电容值。

    Semiconductor Device and Driving Method Thereof
    7.
    发明申请
    Semiconductor Device and Driving Method Thereof 有权
    半导体器件及其驱动方法

    公开(公告)号：US20160172383A1

    公开(公告)日：2016-06-16

    申请号：US14962809

    申请日：2015-12-08

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Shuhei Nagatsuka

    IPC分类号： H01L27/12 ,  H01L29/786

    CPC分类号： H01L27/1225 ,  H01L27/1255

    摘要： The semiconductor device includes a transistor, first to N-th switches (N is a natural number of three or more), and first to (N−1)-th capacitors. A first terminal of the first capacitor (or a J-th capacitor) is electrically connected to a gate of the transistor (or a second terminal of a (J−1)-th capacitor (J is a natural number of two or more and (N−1) or less)). A first (or K-th) potential is supplied to the gate of the transistor through the first switch (or a second terminal of a (K−1)-th capacitor through a K-th switch (K is a natural number of two or more and N or less)). A capacitance value of the first capacitor is preferably equal to a gate capacitance value of the transistor, and a capacitance value of the J-th capacitor is preferably equal to a capacitance value of the (J−1)-th capacitor.

    摘要翻译： 半导体器件包括晶体管，第一至第N开关（N为三个以上的自然数）以及第一至第（N-1）个电容器。 第一电容器（或第J电容器）的第一端子电连接到晶体管的栅极（或第（J-1）个电容器的第二端子（J为两个以上的自然数， （N-1）以下））。 第一（或第K）个电位通过第一开关（或第（K-1）个电容器的第二端子通过第K开关提供给晶体管的栅极（K是自然数为2） 以上且N以下））。 第一电容器的电容值优选等于晶体管的栅极电容值，并且第J电容器的电容值优选等于第（J-1）个电容器的电容值。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08847326B2

    公开(公告)日：2014-09-30

    申请号：US13913591

    申请日：2013-06-10

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Shuhei Nagatsuka

    IPC分类号： H01L27/088 ,  H01L27/108 ,  H01L27/115 ,  H01L27/12 ,  G11C16/04 ,  G11C16/26

    CPC分类号： H01L27/088 ,  G11C16/0433 ,  G11C16/26 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1211 ,  H01L27/1225

    摘要： A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (ta/tb)×(∈ra/∈rb)

    摘要翻译： 具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入周期的数量没有限制。 半导体器件包括存储单元，其包括第一晶体管，第二晶体管和放置在第一晶体管的源极区域或漏极区域与第二晶体管的沟道形成区域之间的绝缘层。 第一晶体管和第二晶体管被设置为至少部分地彼此重叠。 第二晶体管的绝缘层和栅极绝缘层满足下式：（ta / tb）×（∈ra/∈rb）<0.1，其中，ta表示栅极绝缘层的厚度，tb表示第 绝缘层，∈ra表示栅极绝缘层的介电常数，∈rb表示绝缘层的介电常数。

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130256771A1

    公开(公告)日：2013-10-03

    申请号：US13900581

    申请日：2013-05-23

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue

    IPC分类号： H01L27/108

    CPC分类号： H01L29/7869 ,  G11C16/0425 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/78693 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

    摘要： The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

    摘要翻译： 半导体器件包括源极线，位线，信号线，字线，在源极线和位线之间并联连接的存储器单元，通过开关电连接到源极线和位线的第一驱动器电路 元件，通过开关元件电连接到源极线的第二驱动器电路，电连接到信号线的第三驱动电路，以及电连接到字线的第四驱动电路。 存储单元包括第一晶体管，包括第一栅电极，第一源电极和第一漏电极，第二晶体管包括第二栅电极，第二源电极和第二漏极，以及电容器。 第二晶体管包括氧化物半导体材料。