Invention Grant
- Patent Title: Interposer-less stack die interconnect
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Application No.: US14885757Application Date: 2015-10-16
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Publication No.: US09761533B2Publication Date: 2017-09-12
- Inventor: Raghunandan Chaware , Amitava Majumdar , Glenn O'Rourke , Inderjit Singh
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Keith Taboada
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/18 ; H01L25/065 ; H01L23/00

Abstract:
Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.
Public/Granted literature
- US20170110407A1 INTERPOSER-LESS STACK DIE INTERCONNECT Public/Granted day:2017-04-20
Information query
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