公开(公告)号：US09385106B1

公开(公告)日：2016-07-05

申请号：US14444661

申请日：2014-07-28

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Inderjit Singh ,  Glenn O'Rourke ,  Ganesh Hariharan

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/304 ,  H01L23/60

CPC classification number: H01L24/97 ,  H01L21/304 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/60 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A method for providing charge protection to a die during formation of an integrated circuit, includes bonding the die to an interposer to form an unprotected stacked silicon component; encapsulating the unprotected stacked silicon component with a mold compound to cover at least a top surface of the die; grinding the mold compound to reduce a thickness of the mold compound; bonding a carrier wafer to the mold compound; removing the carrier wafer from the mold compound; and removing the mold compound from the top surface of the die after the carrier wafer is removed from the mold compound, to expose the top surface of the die.

Abstract translation: 一种在集成电路形成期间向管芯提供电荷保护的方法，包括将管芯结合到插入件以形成未受保护的堆叠硅部件; 用模具化合物封装未保护的堆叠硅组件以覆盖模具的至少顶表面; 研磨模具化合物以减少模具化合物的厚度; 将载体晶片结合到模具化合物; 从模具化合物中除去载体晶片; 以及在从模具化合物上移除载体晶片之后从模具顶表面去除模具化合物，以露出模具的顶表面。

公开(公告)号：US08900987B1

公开(公告)日：2014-12-02

申请号：US14046846

申请日：2013-10-04

Applicant: Xilinx, Inc.

Inventor： Inderjit Singh ,  Raghunandan Chaware ,  Ganesh Hariharan ,  Glenn O'Rourke

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11001 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/01047

Abstract: A method for removing bumps from incomplete interposer die(s) and/or defective interposer die(s) of an interposer wafer is described. The method includes forming bumps on an interposer wafer; identifying at least one incomplete interposer die and/or at least one defective interposer die of the interposer wafer; and removing bumps from the at least one incomplete interposer die and/or the at least one defective interposer die of the interposer wafer.

Abstract translation: 描述了用于从插入器晶片的不完全插入件裸片和/或插入器裸片的缺陷插入件裸片去除凸块的方法。 该方法包括在插入件晶片上形成凸块; 识别所述插入器晶片的至少一个不完全插入件裸片和/或至少一个缺陷插入器裸片; 以及从所述至少一个不完全插入器裸片和/或所述插入器晶片的所述至少一个缺陷插入器裸片去除凸块。

公开(公告)号：US20140346651A1

公开(公告)日：2014-11-27

申请号：US13899129

申请日：2013-05-21

Applicant: Xilinx, Inc.

Inventor： Qi Xiang ,  Xiao-Yu Li ,  Cinti X. Chen ,  Glenn O'Rourke

IPC: H01L23/60 ,  H01L21/82

CPC classification number: H01L23/60 ,  H01L21/82 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/072 ,  H01L25/18 ,  H01L2924/181 ,  H01L2924/00

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.

Abstract translation: 公开了一般涉及插入件的装置。 在这种装置中，插入器具有多个导体和多个电荷吸引结构。 多个电荷吸引结构是保护至少一个集成电路管芯，以耦合到插入器以提供堆叠的管芯。 多个导体包括多个贯通基板通路。

公开(公告)号：US10707138B1

公开(公告)日：2020-07-07

申请号：US15473395

申请日：2017-03-29

Applicant: Xilinx, Inc.

Inventor： Shiying Xiong ,  Thao H. T. Vo ,  Felino E. Pagaduan ,  Qi Xiang ,  Xiao-Yu Li ,  Glenn O'Rourke

IPC: H01L21/67 ,  H01L21/66 ,  H01L25/00

Abstract: An integrated circuit (IC) chip package assembly apparatus and techniques for assembling IC chip packages are described. For example, a techniques for fabricating an IC package include (A) determining a first package assembly yield (PAY) across a first die pool comprising a first plurality of dies having a performance criteria within a first predefined range; (B) determining a second PAY across a second die pool comprising a second plurality of dies having a performance criteria within a second predefined range of performance criteria that is different than the first predefined range of performance criteria, the second plurality of dies comprising a portion of the first plurality of dies; and (C) generating a final assembly sequence in response to analyzing the first and second PAYs, the final assembly sequence comprising rules for combining dies in accordance with obtaining a higher of the first PAY and the second PAY.

公开(公告)号：US09761533B2

公开(公告)日：2017-09-12

申请号：US14885757

申请日：2015-10-16

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Amitava Majumdar ,  Glenn O'Rourke ,  Inderjit Singh

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/152 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/78 ,  H01L2221/68304 ,  H01L2224/81 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/11 ,  H01L2221/68381 ,  H01L22/00 ,  H01L2224/1181

Abstract: Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

公开(公告)号：US09214433B2

公开(公告)日：2015-12-15

申请号：US13899129

申请日：2013-05-21

Applicant: Xilinx, Inc.

Inventor： Qi Xiang ,  Xiao-Yu Li ,  Cinti X. Chen ,  Glenn O'Rourke

IPC: H01L23/552 ,  H01L23/60 ,  H01L21/82 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L21/82 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/072 ,  H01L25/18 ,  H01L2924/181 ,  H01L2924/00

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.

Abstract translation: 公开了一般涉及插入件的装置。 在这种装置中，插入器具有多个导体和多个电荷吸引结构。 多个电荷吸引结构是保护至少一个集成电路管芯，以耦合到插入器以提供堆叠的管芯。 多个导体包括多个贯通基板通路。

公开(公告)号：US10032682B1

公开(公告)日：2018-07-24

申请号：US15359280

申请日：2016-11-22

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein ,  Raghunandan Chaware ,  Glenn O'Rourke

IPC: H01L21/66 ,  H01L21/78 ,  H01L21/56 ,  H01L23/00

Abstract: Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an interposer. One example method generally includes testing a plurality of IC dies disposed on a wafer; disposing one or more connectivity layers above the plurality of IC dies, the one or more connectivity layers comprising one or more electrical conductors configured to connect together two or more of the plurality of dies in each of one or more groups of the IC dies; dicing the wafer having the one or more connectivity layers disposed above the plurality of dies into sets, each set comprising one or more of the plurality of dies, wherein the dicing is based on the one or more groups having IC dies that passed the testing; and packaging at least a portion of the sets of dies.

公开(公告)号：US20170110407A1

公开(公告)日：2017-04-20

申请号：US14885757

申请日：2015-10-16

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Amitava Majumdar ,  Glenn O'Rourke ,  Inderjit Singh

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/152 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/78 ,  H01L2221/68304 ,  H01L2224/81 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/11 ,  H01L2221/68381 ,  H01L22/00 ,  H01L2224/1181

Abstract: Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

公开(公告)号：US09341668B1

公开(公告)日：2016-05-17

申请号：US14242760

申请日：2014-04-01

Applicant: Xilinx, Inc.

Inventor： Ganesh Hariharan ,  Raghunandan Chaware ,  Glenn O'Rourke ,  Inderjit Singh ,  Eric J. Thorne ,  David E. Schweigler

IPC: G01R31/00 ,  G01R31/26 ,  G01R1/04

CPC classification number: G01R31/2889 ,  G01R1/0416

Abstract: A testable circuit arrangement includes an integrated circuit (IC) package. The IC package includes a package substrate, an interposer mounted directly on the package substrate with level 1 interconnects, and at least one IC die mounted directly on the interposer with level 0 interconnects. The package substrate of the IC package is mounted directly on a connector board with a soldered ball grid array of level 2 interconnects. The level 0, level 1, and level 2 interconnects include respective power, configuration, and test interconnects. Power, configuration, and test terminals of the connector board are coupled to the power, configuration, and test interconnects of the level 2 interconnects.

Abstract translation: 可测试电路装置包括集成电路（IC）封装。 IC封装包括封装衬底，直接安装在具有级别1互连的封装衬底上的插入件以及直接安装在具有0级互连的插入器上的至少一个IC管芯。 IC封装的封装基板直接安装在具有2级互连的焊接球栅格阵列的连接器板上。 0级，1级和2级互连包括各自的功率，配置和测试互连。 连接器板的电源，配置和测试端子耦合到2级互连的电源，配置和测试互连。

公开(公告)号：US09865567B1

公开(公告)日：2018-01-09

申请号：US15423303

申请日：2017-02-02

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Ganesh Hariharan ,  Inderjit Singh ,  Amitava Majumdar ,  Glenn O'Rourke

IPC: H01L21/58 ,  H01L25/065 ,  H01L25/00 ,  H01L21/82 ,  H01L21/66 ,  H01L23/00 ,  H01L21/56 ,  H01L25/16

CPC classification number: H01L25/0655 ,  H01L21/563 ,  H01L21/82 ,  H01L22/14 ,  H01L22/20 ,  H01L24/17 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/17181

Abstract: An example method of manufacturing a semiconductor assembly includes: forming first integrated circuit (IC) dies and dummy dies; forming an interposer wafer including a top side having first mounting sites for the first IC dies and second mounting sites for second IC dies; attaching the first IC dies to the interposer wafer at the first mounting sites and the dummy dies to the interposer wafer at the second mounting sites; processing a backside and the top side of the interposer wafer; removing the dummy dies from the top side of the interposer wafer to expose the second mounting sites; and attaching the second IC dies to the interposer wafer at the exposed second mounting sites.