- 专利标题: Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
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申请号: US14524693申请日: 2014-10-27
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公开(公告)号: US09768056B2公开(公告)日: 2017-09-19
- 发明人: Igor Peidous , Illaria Katia Marianna Pellicano
- 申请人: SunEdison Semiconductor Limited (UEN201334164H)
- 申请人地址: SG Singapore
- 专利权人: SunEdison Semiconductor Limited (UEN201334164H)
- 当前专利权人: SunEdison Semiconductor Limited (UEN201334164H)
- 当前专利权人地址: SG Singapore
- 代理机构: Armstrong Teasdale LLP
- 主分类号: H01L21/02
- IPC分类号: H01L21/02 ; H01L21/762
摘要:
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
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