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公开(公告)号：US09768056B2
公开(公告)日：2017-09-19
申请号：US14524693
申请日：2014-10-27
IPC分类号： H01L21/02 , H01L21/762
CPC分类号： H01L21/76251 , H01L21/02238 , H01L21/02529 , H01L21/02532 , H01L21/0262
摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
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2.发明申请公开(公告)号：US20170365506A1
公开(公告)日：2017-12-21
申请号：US15675001
申请日：2017-08-11
IPC分类号： H01L21/762 , H01L21/02
CPC分类号： H01L21/76251 , H01L21/02238 , H01L21/02529 , H01L21/02532 , H01L21/0262
摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
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3.发明申请METHOD OF MANUFACTURING HIGH RESISTIVITY SOI WAFERS WITH CHARGE TRAPPING LAYERS BASED ON TERMINATED SI DEPOSITION 有权基于终止沉积法制备具有电荷捕获层的高电阻SOI波形的方法公开(公告)号：US20150115480A1
公开(公告)日：2015-04-30
申请号：US14524693
申请日：2014-10-27
IPC分类号： H01L21/762 , H01L29/16 , H01L21/02
CPC分类号： H01L21/76251 , H01L21/02238 , H01L21/02529 , H01L21/02532 , H01L21/0262
摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
摘要翻译： 提供了在制造绝缘体上硅器件时制备单晶半导体处理晶片的方法。 该方法包括在高电阻率单晶半导体处理晶片的电介质层上形成多层钝化的半导体层。 该方法还包括在钝化半导体层的多层上形成半导体氧化物层。 钝化半导体层的多层包括适合用作绝缘体半导体结构中的高电阻率衬底和掩埋氧化物层之间的电荷俘获层的材料。
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公开(公告)号：US10083855B2
公开(公告)日：2018-09-25
申请号：US15675001
申请日：2017-08-11
IPC分类号： H01L21/762 , H01L21/02
CPC分类号： H01L21/76251 , H01L21/02238 , H01L21/02529 , H01L21/02532 , H01L21/0262
摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
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