Invention Grant
- Patent Title: Methods of forming wiring structures including a plurality of metal layers
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Application No.: US15000302Application Date: 2016-01-19
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Publication No.: US09773699B2Publication Date: 2017-09-26
- Inventor: Jong-Jin Lee , Rak-Hwan Kim , Byung-Hee Kim , Jin-Nam Kim , Tsukasa Matsuda , Wan-Soo Park , Nae-In Lee , Jae-Won Chang , Eun-Ji Jung , Jeong-Ok Cha , Jae-Won Hwang , Jung-Ha Hwang
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2015-0047026 20150402
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/768 ; H01L23/522 ; H01L23/528 ; H01L23/532
Abstract:
In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.
Public/Granted literature
- US20160293484A1 METHODS OF FORMING WIRING STRUCTURES Public/Granted day:2016-10-06
Information query
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