公开(公告)号：US10332791B2

公开(公告)日：2019-06-25

申请号：US15805865

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Yun Jeon ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Kyoung-Hee Nam ,  Jong-Jin Lee ,  Jae-Won Hwang

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/288 ,  H01L23/528 ,  H01L23/522 ,  H01L21/285

Abstract: A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench. The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer. The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.

公开(公告)号：US09773699B2

公开(公告)日：2017-09-26

申请号：US15000302

申请日：2016-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76882 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238

Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

公开(公告)号：US20180158730A1

公开(公告)日：2018-06-07

申请号：US15805865

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Yun Jeon ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Kyoung-Hee Nam ,  Jong-Jin Lee ,  Jae-Won Hwang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76865 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/2885 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238

Abstract: A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench, The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer, The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.